Commit 8be7dfc6 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'coresight-next-v6.1' of... 

Merge tag 'coresight-next-v6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux

 into char-misc-next

Suzuki writes:
  "coresight: Changes for v6.1

   Coresight trace subsystem updates for v6.1 includes:
     - Support for HiSilicon PTT trace
     - Coresight cleanup of sysfs accessor functions, reduced
       code size.
     - Expose coresight timestamp source for ETMv4+
     - DT binding updates to include missing properties
     - Minor documentation, Kconfig text fixes.

   Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com&gt;">

* tag 'coresight-next-v6.1' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux:
  hwtracing: hisi_ptt: Fix up for "iommu/dma: Make header private"
  MAINTAINERS: Add maintainer for HiSilicon PTT driver
  docs: trace: Add HiSilicon PTT device driver documentation
  hwtracing: hisi_ptt: Add tune function support for HiSilicon PCIe Tune and Trace device
  hwtracing: hisi_ptt: Add trace function support for HiSilicon PCIe Tune and Trace device
  iommu/arm-smmu-v3: Make default domain type of HiSilicon PTT device to identity
  coresight: cti-sysfs: Mark coresight_cti_reg_store() as __maybe_unused
  coresight: Make new csdev_access offsets unsigned
  coresight: cti-sysfs: Re-use same functions for similar sysfs register accessors
  coresight: Re-use same function for similar sysfs register accessors
  coresight: Simplify sysfs accessors by using csdev_access abstraction
  coresight: Remove unused function parameter
  coresight: etm4x: docs: Add documentation for 'ts_source' sysfs interface
  coresight: etm4x: Expose default timestamp source in sysfs
  dt-bindings: arm: coresight-tmc: Add 'iommu' property
  dt-bindings: arm: coresight: Add 'power-domains' property
  coresight: docs: Fix a broken reference
  coresight: trbe: fix Kconfig "its" grammar
parents 4ba028e4 5fc1531d

Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x

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@@ -516,3 +516,11 @@ Contact: Mathieu Poirier <mathieu.poirier@linaro.org> 
Description:	(Read) Returns the number of special conditional P1 right-hand keys

		that the trace unit can use (0x194).  The value is taken

		directly from the HW.



What:		/sys/bus/coresight/devices/etm<N>/ts_source

Date:		October 2022

KernelVersion:	6.1

Contact:	Mathieu Poirier <mathieu.poirier@linaro.org> or Suzuki K Poulose <suzuki.poulose@arm.com>

Description:	(Read) When FEAT_TRF is implemented, value of TRFCR_ELx.TS used for

		trace session. Otherwise -1 indicates an unknown time source. Check

		trcidr0.tssize to see if a global timestamp is available.

Documentation/ABI/testing/sysfs-devices-hisi_ptt

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What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/tune

Date:		October 2022

KernelVersion:	6.1

Contact:	Yicong Yang <yangyicong@hisilicon.com>

Description:	This directory contains files for tuning the PCIe link

		parameters(events). Each file is named after the event

		of the PCIe link.



		See Documentation/trace/hisi-ptt.rst for more information.



What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_cpl

Date:		October 2022

KernelVersion:	6.1

Contact:	Yicong Yang <yangyicong@hisilicon.com>

Description:	(RW) Controls the weight of Tx completion TLPs, which influence

		the proportion of outbound completion TLPs on the PCIe link.

		The available tune data is [0, 1, 2]. Writing a negative value

		will return an error, and out of range values will be converted

		to 2. The value indicates a probable level of the event.



What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_np

Date:		October 2022

KernelVersion:	6.1

Contact:	Yicong Yang <yangyicong@hisilicon.com>

Description:	(RW) Controls the weight of Tx non-posted TLPs, which influence

		the proportion of outbound non-posted TLPs on the PCIe link.

		The available tune data is [0, 1, 2]. Writing a negative value

		will return an error, and out of range values will be converted

		to 2. The value indicates a probable level of the event.



What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/qos_tx_p

Date:		October 2022

KernelVersion:	6.1

Contact:	Yicong Yang <yangyicong@hisilicon.com>

Description:	(RW) Controls the weight of Tx posted TLPs, which influence the

		proportion of outbound posted TLPs on the PCIe link.

		The available tune data is [0, 1, 2]. Writing a negative value

		will return an error, and out of range values will be converted

		to 2. The value indicates a probable level of the event.



What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/rx_alloc_buf_level

Date:		October 2022

KernelVersion:	6.1

Contact:	Yicong Yang <yangyicong@hisilicon.com>

Description:	(RW) Control the allocated buffer watermark for inbound packets.

		The packets will be stored in the buffer first and then transmitted

		either when the watermark reached or when timed out.

		The available tune data is [0, 1, 2]. Writing a negative value

		will return an error, and out of range values will be converted

		to 2. The value indicates a probable level of the event.



What:		/sys/devices/hisi_ptt<sicl_id>_<core_id>/tune/tx_alloc_buf_level

Date:		October 2022

KernelVersion:	6.1

Contact:	Yicong Yang <yangyicong@hisilicon.com>

Description:	(RW) Control the allocated buffer watermark of outbound packets.

		The packets will be stored in the buffer first and then transmitted

		either when the watermark reached or when timed out.

		The available tune data is [0, 1, 2]. Writing a negative value

		will return an error, and out of range values will be converted

		to 2. The value indicates a probable level of the event.

Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml

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@@ -61,6 +61,9 @@ properties: 
    maxItems: 1

    description: Address translation error interrupt



  power-domains:

    maxItems: 1



  in-ports:

    $ref: /schemas/graph.yaml#/properties/ports

    additionalProperties: false

Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml

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@@ -98,6 +98,9 @@ properties: 
      base cti node if compatible string arm,coresight-cti-v8-arch is used,

      or may appear in a trig-conns child node when appropriate.



  power-domains:

    maxItems: 1



  arm,cti-ctm-id:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml

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@@ -54,6 +54,9 @@ properties: 
      - const: apb_pclk

      - const: atclk



  power-domains:

    maxItems: 1



  in-ports:

    $ref: /schemas/graph.yaml#/properties/ports