Commit 8bdf2023 authored by Michael Ellerman's avatar Michael Ellerman
Browse files

Merge branch 'next' of git://git.denx.de/linux-denx-agust into next 

MPC5xxx updates from Anatolij:

"Highlights include a driver for MPC512x LocalPlus Bus FIFO with its
device tree binding documentation, mpc512x device tree updates and some
minor fixes."
parents 3b0e21ec 39e69f55

Documentation/devicetree/bindings/powerpc/fsl/mpc512x_lpbfifo.txt

0 → 100644
+21 −0
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Freescale MPC512x LocalPlus Bus FIFO (called SCLPC in the Reference Manual)



Required properties:

- compatible: should be "fsl,mpc512x-lpbfifo";

- reg: should contain the offset and length of SCLPC register set;

- interrupts: should contain the interrupt specifier for SCLPC; syntax of an

    interrupt client node is described in interrupt-controller/interrupts.txt;

- dmas: should contain the DMA specifier for SCLPC as described at

    dma/dma.txt and dma/mpc512x-dma.txt;

- dma-names: should be "rx-tx";



Example:



	sclpc@10100 {

		compatible = "fsl,mpc512x-lpbfifo";

		reg = <0x10100 0x50>;

		interrupts = <7 0x8>;

		dmas = <&dma0 26>;

		dma-names = "rx-tx";

	};

arch/powerpc/boot/dts/mpc5121.dtsi

+9 −2
Original line number Diff line number Diff line
@@ -77,7 +77,6 @@ 
		#address-cells = <2>;

		#size-cells = <1>;

		reg = <0x80000020 0x40>;

		interrupts = <7 0x8>;

		ranges = <0x0 0x0 0xfc000000 0x04000000>;

	};
@@ -329,7 +328,15 @@ 
		/* LocalPlus controller */

		lpc@10000 {

			compatible = "fsl,mpc5121-lpc";

			reg = <0x10000 0x200>;

			reg = <0x10000 0x100>;

		};



		sclpc@10100 {

			compatible = "fsl,mpc512x-lpbfifo";

			reg = <0x10100 0x50>;

			interrupts = <7 0x8>;

			dmas = <&dma0 26>;

			dma-names = "rx-tx";

		};



		pata@10200 {

arch/powerpc/boot/dts/mpc5125twr.dts

+10 −1
Original line number Diff line number Diff line
@@ -246,6 +246,14 @@ 
			status = "disabled";

		};



		sclpc@10100 {

			compatible = "fsl,mpc512x-lpbfifo";

			reg = <0x10100 0x50>;

			interrupts = <7 0x8>;

			dmas = <&dma0 26>;

			dma-names = "rx-tx";

		};



		// 5125 PSCs are not 52xx or 5121 PSC compatible

		// PSC1 uart0 aka ttyPSC0

		serial@11100 {
@@ -279,10 +287,11 @@ 
			clock-names = "ipg";

		};



		dma@14000 {

		dma0: dma@14000 {

			compatible = "fsl,mpc5121-dma"; // BSP name: "mpc512x-dma2"

			reg = <0x14000 0x1800>;

			interrupts = <65 0x8>;

			#dma-cells = <1>;

		};

	};

};

arch/powerpc/configs/mpc512x_defconfig

+1 −0
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@@ -112,6 +112,7 @@ CONFIG_RTC_DRV_M41T80=y 
CONFIG_RTC_DRV_MPC5121=y

CONFIG_DMADEVICES=y

CONFIG_MPC512X_DMA=y

CONFIG_MPC512x_LPBFIFO=y

CONFIG_EXT2_FS=y

CONFIG_EXT2_FS_XIP=y

CONFIG_EXT3_FS=y

arch/powerpc/include/asm/mpc5121.h

+59 −0
Original line number Diff line number Diff line
@@ -60,4 +60,63 @@ struct mpc512x_lpc { 


int mpc512x_cs_config(unsigned int cs, u32 val);



/*

 * SCLPC Module (LPB FIFO)

 */

struct mpc512x_lpbfifo {

	u32	pkt_size;	/* SCLPC Packet Size Register */

	u32	start_addr;	/* SCLPC Start Address Register */

	u32	ctrl;		/* SCLPC Control Register */

	u32	enable;		/* SCLPC Enable Register */

	u32	reserved1;

	u32	status;		/* SCLPC Status Register */

	u32	bytes_done;	/* SCLPC Bytes Done Register */

	u32	emb_sc;		/* EMB Share Counter Register */

	u32	emb_pc;		/* EMB Pause Control Register */

	u32	reserved2[7];

	u32	data_word;	/* LPC RX/TX FIFO Data Word Register */

	u32	fifo_status;	/* LPC RX/TX FIFO Status Register */

	u32	fifo_ctrl;	/* LPC RX/TX FIFO Control Register */

	u32	fifo_alarm;	/* LPC RX/TX FIFO Alarm Register */

};



#define MPC512X_SCLPC_START		(1 << 31)

#define MPC512X_SCLPC_CS(x)		(((x) & 0x7) << 24)

#define MPC512X_SCLPC_FLUSH		(1 << 17)

#define MPC512X_SCLPC_READ		(1 << 16)

#define MPC512X_SCLPC_DAI		(1 << 8)

#define MPC512X_SCLPC_BPT(x)		((x) & 0x3f)

#define MPC512X_SCLPC_RESET		(1 << 24)

#define MPC512X_SCLPC_FIFO_RESET	(1 << 16)

#define MPC512X_SCLPC_ABORT_INT_ENABLE	(1 << 9)

#define MPC512X_SCLPC_NORM_INT_ENABLE	(1 << 8)

#define MPC512X_SCLPC_ENABLE		(1 << 0)

#define MPC512X_SCLPC_SUCCESS		(1 << 24)

#define MPC512X_SCLPC_FIFO_CTRL(x)	(((x) & 0x7) << 24)

#define MPC512X_SCLPC_FIFO_ALARM(x)	((x) & 0x3ff)



enum lpb_dev_portsize {

	LPB_DEV_PORTSIZE_UNDEFINED = 0,

	LPB_DEV_PORTSIZE_1_BYTE = 1,

	LPB_DEV_PORTSIZE_2_BYTES = 2,

	LPB_DEV_PORTSIZE_4_BYTES = 4,

	LPB_DEV_PORTSIZE_8_BYTES = 8

};



enum mpc512x_lpbfifo_req_dir {

	MPC512X_LPBFIFO_REQ_DIR_READ,

	MPC512X_LPBFIFO_REQ_DIR_WRITE

};



struct mpc512x_lpbfifo_request {

	phys_addr_t dev_phys_addr; /* physical address of some device on LPB */

	void *ram_virt_addr; /* virtual address of some region in RAM */

	u32 size;

	enum lpb_dev_portsize portsize;

	enum mpc512x_lpbfifo_req_dir dir;

	void (*callback)(struct mpc512x_lpbfifo_request *);

};



int mpc512x_lpbfifo_submit(struct mpc512x_lpbfifo_request *req);



#endif /* __ASM_POWERPC_MPC5121_H__ */