Unverified Commit 8bb84ca8 authored by Pierre-Louis Bossart's avatar Pierre-Louis Bossart Committed by Mark Brown
Browse files

ASoC: SOF: Intel: move ELH chip info 



ELH is a derivative of TGL, so it should be exposed in tgl.c for
consistency.

No functional change.

Reviewed-by: default avatarRander Wang <rander.wang@intel.com>
Reviewed-by: default avatarKai Vehmanen <kai.vehmanen@linux.intel.com>
Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20210322163728.16616-9-pierre-louis.bossart@linux.intel.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent d3aa96bf

sound/soc/sof/intel/cnl.c

+0 −16
Original line number Diff line number Diff line
@@ -350,22 +350,6 @@ const struct sof_intel_dsp_desc cnl_chip_info = { 
};

EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);



const struct sof_intel_dsp_desc ehl_chip_info = {

	/* Elkhartlake */

	.cores_num = 4,

	.init_core_mask = 1,

	.host_managed_cores_mask = BIT(0),

	.ipc_req = CNL_DSP_REG_HIPCIDR,

	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,

	.ipc_ack = CNL_DSP_REG_HIPCIDA,

	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,

	.ipc_ctl = CNL_DSP_REG_HIPCCTL,

	.rom_init_timeout	= 300,

	.ssp_count = ICL_SSP_COUNT,

	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

};

EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);



const struct sof_intel_dsp_desc jsl_chip_info = {

	/* Jasperlake */

	.cores_num = 2,

sound/soc/sof/intel/tgl.c

+16 −0
Original line number Diff line number Diff line
@@ -156,6 +156,22 @@ const struct sof_intel_dsp_desc tglh_chip_info = { 
};

EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);



const struct sof_intel_dsp_desc ehl_chip_info = {

	/* Elkhartlake */

	.cores_num = 4,

	.init_core_mask = 1,

	.host_managed_cores_mask = BIT(0),

	.ipc_req = CNL_DSP_REG_HIPCIDR,

	.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,

	.ipc_ack = CNL_DSP_REG_HIPCIDA,

	.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,

	.ipc_ctl = CNL_DSP_REG_HIPCCTL,

	.rom_init_timeout	= 300,

	.ssp_count = ICL_SSP_COUNT,

	.ssp_base_offset = CNL_SSP_BASE_OFFSET,

};

EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);



const struct sof_intel_dsp_desc adls_chip_info = {

	/* Alderlake-S */

	.cores_num = 2,