Commit 8bb289bb authored by Oleksij Rempel's avatar Oleksij Rempel Committed by Abel Vesa
Browse files

clk: imx6q: add ethernet refclock mux support 



Add ethernet refclock mux support and set it to internal clock by
default. This configuration will not affect existing boards since
machine code currently overwrites this default.

The machine code will be fixed in a separate patch.

Signed-off-by: default avatarOleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Signed-off-by: default avatarAbel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230131084642.709385-3-o.rempel@pengutronix.de
parent ee394f63

drivers/clk/imx/clk-imx6q.c

+13 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/clk-provider.h>

#include <linux/err.h>

#include <linux/io.h>

#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_irq.h>
@@ -115,6 +116,10 @@ static struct clk_div_table video_div_table[] = { 
	{ /* sentinel */ }

};



static const char * enet_ref_sels[] = { "enet_ref", "enet_ref_pad", };

static const u32 enet_ref_sels_table[] = { IMX6Q_GPR1_ENET_CLK_SEL_ANATOP, IMX6Q_GPR1_ENET_CLK_SEL_PAD };

static const u32 enet_ref_sels_table_mask = IMX6Q_GPR1_ENET_CLK_SEL_ANATOP;



static unsigned int share_count_esai;

static unsigned int share_count_asrc;

static unsigned int share_count_ssi1;
@@ -908,6 +913,12 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
	if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)

		hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER];



	hws[IMX6QDL_CLK_ENET_REF_PAD] = imx6q_obtain_fixed_clk_hw(ccm_node, "enet_ref_pad", 0);



	hws[IMX6QDL_CLK_ENET_REF_SEL] = imx_clk_gpr_mux("enet_ref_sel", "fsl,imx6q-iomuxc-gpr",

				IOMUXC_GPR1, enet_ref_sels, ARRAY_SIZE(enet_ref_sels),

				enet_ref_sels_table, enet_ref_sels_table_mask);



	imx_check_clk_hws(hws, IMX6QDL_CLK_END);



	of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
@@ -974,6 +985,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) 
			       hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);

	}



	clk_set_parent(hws[IMX6QDL_CLK_ENET_REF_SEL]->clk, hws[IMX6QDL_CLK_ENET_REF]->clk);



	imx_register_uart_clocks();

}

CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);

include/dt-bindings/clock/imx6qdl-clock.h

+3 −1
Original line number Diff line number Diff line
@@ -273,6 +273,8 @@ 
#define IMX6QDL_CLK_MMDC_P0_IPG			263

#define IMX6QDL_CLK_DCIC1			264

#define IMX6QDL_CLK_DCIC2			265

#define IMX6QDL_CLK_END				266

#define IMX6QDL_CLK_ENET_REF_SEL		266

#define IMX6QDL_CLK_ENET_REF_PAD		267

#define IMX6QDL_CLK_END				268



#endif /* __DT_BINDINGS_CLOCK_IMX6QDL_H */