Commit 8baef638 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2021-07-23' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular fixes - a bunch of amdgpu fixes are the main thing mostly for
  the new gpus. There is also some i915 reverts for older changes that
  were having some unwanted side effects. One nouveau fix for a report
  regressions, and otherwise just some misc fixes.

  core:
   - fix for non-drm ioctls on drm fd

  panel:
   - avoid double free

  ttm:
   - refcounting fix
   - NULL checks

  amdgpu:
   - Yellow Carp updates
   - Add some Yellow Carp DIDs
   - Beige Goby updates
   - CIK 10bit 4K regression fix
   - GFX10 golden settings updates
   - eDP panel regression fix
   - Misc display fixes
   - Aldebaran fix
   - fix COW checks

  nouveau:
   - init BO GEM fields

  i915:
   - revert async command parsing
   - revert fence error propogation
   - GVT fix for shadow ppgtt

  vc4:
   - fix interrupt handling"

* tag 'drm-fixes-2021-07-23' of git://anongit.freedesktop.org/drm/drm: (34 commits)
  drm/panel: raspberrypi-touchscreen: Prevent double-free
  drm/amdgpu - Corrected the video codecs array name for yellow carp
  drm/amd/display: Fix ASSR regression on embedded panels
  drm/amdgpu: add yellow carp pci id (v2)
  drm/amdgpu: update yellow carp external rev_id handling
  drm/amd/pm: Support board calibration on aldebaran
  drm/amd/display: change zstate allow msg condition
  drm/amd/display: Populate dtbclk entries for dcn3.02/3.03
  drm/amd/display: Line Buffer changes
  drm/amd/display: Remove MALL function from DCN3.1
  drm/amd/display: Only set default brightness for OLED
  drm/amd/display: Update bounding box for DCN3.1
  drm/amd/display: Query VCO frequency from register for DCN3.1
  drm/amd/display: Populate socclk entries for dcn3.02/3.03
  drm/amd/display: Fix max vstartup calculation for modes with borders
  drm/amd/display: implement workaround for riommu related hang
  drm/amd/display: Fix comparison error in dcn21 DML
  drm/i915: Correct the docs for intel_engine_cmd_parser
  drm/ttm: add missing NULL checks
  drm/ttm: Force re-init if ttm_global_init() fails
  ...
parents e08100fe 2e41a669

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+7 −0
Original line number Diff line number Diff line
@@ -619,6 +619,13 @@ struct amdgpu_video_codec_info { 
	u32 max_level;

};



#define codec_info_build(type, width, height, level) \

			 .codec_type = type,\

			 .max_width = width,\

			 .max_height = height,\

			 .max_pixels_per_frame = height * width,\

			 .max_level = level,



struct amdgpu_video_codecs {

	const u32 codec_count;

	const struct amdgpu_video_codec_info *codec_array;

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+4 −0
Original line number Diff line number Diff line
@@ -1190,6 +1190,10 @@ static const struct pci_device_id pciidlist[] = { 
	/* Van Gogh */

	{0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},



	/* Yellow Carp */

	{0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},

	{0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},



	/* Navy_Flounder */

	{0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},

	{0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},

drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

+9 −0
Original line number Diff line number Diff line
@@ -255,6 +255,15 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str 
	if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)

		return -EPERM;



	/* Workaround for Thunk bug creating PROT_NONE,MAP_PRIVATE mappings

	 * for debugger access to invisible VRAM. Should have used MAP_SHARED

	 * instead. Clearing VM_MAYWRITE prevents the mapping from ever

	 * becoming writable and makes is_cow_mapping(vm_flags) false.

	 */

	if (is_cow_mapping(vma->vm_flags) &&

	    !(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC)))

		vma->vm_flags &= ~VM_MAYWRITE;



	return drm_gem_ttm_mmap(obj, vma);

}

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

+3 −0
Original line number Diff line number Diff line
@@ -3300,6 +3300,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)

};
@@ -3379,6 +3380,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
@@ -3445,6 +3447,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = 
	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),

	SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)

drivers/gpu/drm/amd/amdgpu/nv.c

+50 −198
Original line number Diff line number Diff line
@@ -64,32 +64,13 @@ 
#include "smuio_v11_0.h"

#include "smuio_v11_0_6.h"



#define codec_info_build(type, width, height, level) \

			 .codec_type = type,\

			 .max_width = width,\

			 .max_height = height,\

			 .max_pixels_per_frame = height * width,\

			 .max_level = level,



static const struct amd_ip_funcs nv_common_ip_funcs;



/* Navi */

static const struct amdgpu_video_codec_info nv_video_codecs_encode_array[] =

{

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,

		.max_width = 4096,

		.max_height = 2304,

		.max_pixels_per_frame = 4096 * 2304,

		.max_level = 0,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,

		.max_width = 4096,

		.max_height = 2304,

		.max_pixels_per_frame = 4096 * 2304,

		.max_level = 0,

	},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},

};



static const struct amdgpu_video_codecs nv_video_codecs_encode =
@@ -101,55 +82,13 @@ static const struct amdgpu_video_codecs nv_video_codecs_encode = 
/* Navi1x */

static const struct amdgpu_video_codec_info nv_video_codecs_decode_array[] =

{

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 3,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 5,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 52,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 4,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,

		.max_width = 8192,

		.max_height = 4352,

		.max_pixels_per_frame = 8192 * 4352,

		.max_level = 186,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 0,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,

		.max_width = 8192,

		.max_height = 4352,

		.max_pixels_per_frame = 8192 * 4352,

		.max_level = 0,

	},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},

};



static const struct amdgpu_video_codecs nv_video_codecs_decode =
@@ -161,62 +100,14 @@ static const struct amdgpu_video_codecs nv_video_codecs_decode = 
/* Sienna Cichlid */

static const struct amdgpu_video_codec_info sc_video_codecs_decode_array[] =

{

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 3,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 5,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 52,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 4,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,

		.max_width = 8192,

		.max_height = 4352,

		.max_pixels_per_frame = 8192 * 4352,

		.max_level = 186,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 0,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,

		.max_width = 8192,

		.max_height = 4352,

		.max_pixels_per_frame = 8192 * 4352,

		.max_level = 0,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,

		.max_width = 8192,

		.max_height = 4352,

		.max_pixels_per_frame = 8192 * 4352,

		.max_level = 0,

	},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},

};



static const struct amdgpu_video_codecs sc_video_codecs_decode =
@@ -228,80 +119,20 @@ static const struct amdgpu_video_codecs sc_video_codecs_decode = 
/* SRIOV Sienna Cichlid, not const since data is controlled by host */

static struct amdgpu_video_codec_info sriov_sc_video_codecs_encode_array[] =

{

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,

		.max_width = 4096,

		.max_height = 2304,

		.max_pixels_per_frame = 4096 * 2304,

		.max_level = 0,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,

		.max_width = 4096,

		.max_height = 2304,

		.max_pixels_per_frame = 4096 * 2304,

		.max_level = 0,

	},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},

};



static struct amdgpu_video_codec_info sriov_sc_video_codecs_decode_array[] =

{

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 3,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 5,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 52,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 4,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC,

		.max_width = 8192,

		.max_height = 4352,

		.max_pixels_per_frame = 8192 * 4352,

		.max_level = 186,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG,

		.max_width = 4096,

		.max_height = 4096,

		.max_pixels_per_frame = 4096 * 4096,

		.max_level = 0,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9,

		.max_width = 8192,

		.max_height = 4352,

		.max_pixels_per_frame = 8192 * 4352,

		.max_level = 0,

	},

	{

		.codec_type = AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1,

		.max_width = 8192,

		.max_height = 4352,

		.max_pixels_per_frame = 8192 * 4352,

		.max_level = 0,

	},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2, 4096, 4906, 3)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4, 4096, 4906, 5)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1, 4096, 4906, 4)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},

};



static struct amdgpu_video_codecs sriov_sc_video_codecs_encode =
@@ -333,6 +164,19 @@ static const struct amdgpu_video_codecs bg_video_codecs_encode = { 
	.codec_array = NULL,

};



/* Yellow Carp*/

static const struct amdgpu_video_codec_info yc_video_codecs_decode_array[] = {

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4906, 52)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},

	{codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},

};



static const struct amdgpu_video_codecs yc_video_codecs_decode = {

	.codec_count = ARRAY_SIZE(yc_video_codecs_decode_array),

	.codec_array = yc_video_codecs_decode_array,

};



static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,

				 const struct amdgpu_video_codecs **codecs)

{
@@ -353,12 +197,17 @@ static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode, 
	case CHIP_NAVY_FLOUNDER:

	case CHIP_DIMGREY_CAVEFISH:

	case CHIP_VANGOGH:

	case CHIP_YELLOW_CARP:

		if (encode)

			*codecs = &nv_video_codecs_encode;

		else

			*codecs = &sc_video_codecs_decode;

		return 0;

	case CHIP_YELLOW_CARP:

		if (encode)

			*codecs = &nv_video_codecs_encode;

		else

			*codecs = &yc_video_codecs_decode;

		return 0;

	case CHIP_BEIGE_GOBY:

		if (encode)

			*codecs = &bg_video_codecs_encode;
@@ -1387,6 +1236,9 @@ static int nv_common_early_init(void *handle) 
			AMD_PG_SUPPORT_VCN |

			AMD_PG_SUPPORT_VCN_DPG |

			AMD_PG_SUPPORT_JPEG;

		if (adev->pdev->device == 0x1681)

			adev->external_rev_id = adev->rev_id + 0x19;

		else

			adev->external_rev_id = adev->rev_id + 0x01;

		break;

	default: