Loading drivers/gpu/ipu-v3/ipu-ic.c +1 −1 Original line number Diff line number Diff line Loading @@ -619,7 +619,7 @@ int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel, ipu_ic_write(ic, ic_idmac_2, IC_IDMAC_2); ipu_ic_write(ic, ic_idmac_3, IC_IDMAC_3); if (rot >= IPU_ROTATE_90_RIGHT) if (ipu_rot_mode_is_irt(rot)) ic->rotation = true; unlock: Loading include/video/imx-ipu-v3.h +15 −7 Original line number Diff line number Diff line Loading @@ -63,17 +63,25 @@ enum ipu_csi_dest { /* * Enumeration of IPU rotation modes */ #define IPU_ROT_BIT_VFLIP (1 << 0) #define IPU_ROT_BIT_HFLIP (1 << 1) #define IPU_ROT_BIT_90 (1 << 2) enum ipu_rotate_mode { IPU_ROTATE_NONE = 0, IPU_ROTATE_VERT_FLIP, IPU_ROTATE_HORIZ_FLIP, IPU_ROTATE_180, IPU_ROTATE_90_RIGHT, IPU_ROTATE_90_RIGHT_VFLIP, IPU_ROTATE_90_RIGHT_HFLIP, IPU_ROTATE_90_LEFT, IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP, IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP, IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP), IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90, IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP), IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP), IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP), }; /* 90-degree rotations require the IRT unit */ #define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0) enum ipu_color_space { IPUV3_COLORSPACE_RGB, IPUV3_COLORSPACE_YUV, Loading Loading
drivers/gpu/ipu-v3/ipu-ic.c +1 −1 Original line number Diff line number Diff line Loading @@ -619,7 +619,7 @@ int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel, ipu_ic_write(ic, ic_idmac_2, IC_IDMAC_2); ipu_ic_write(ic, ic_idmac_3, IC_IDMAC_3); if (rot >= IPU_ROTATE_90_RIGHT) if (ipu_rot_mode_is_irt(rot)) ic->rotation = true; unlock: Loading
include/video/imx-ipu-v3.h +15 −7 Original line number Diff line number Diff line Loading @@ -63,17 +63,25 @@ enum ipu_csi_dest { /* * Enumeration of IPU rotation modes */ #define IPU_ROT_BIT_VFLIP (1 << 0) #define IPU_ROT_BIT_HFLIP (1 << 1) #define IPU_ROT_BIT_90 (1 << 2) enum ipu_rotate_mode { IPU_ROTATE_NONE = 0, IPU_ROTATE_VERT_FLIP, IPU_ROTATE_HORIZ_FLIP, IPU_ROTATE_180, IPU_ROTATE_90_RIGHT, IPU_ROTATE_90_RIGHT_VFLIP, IPU_ROTATE_90_RIGHT_HFLIP, IPU_ROTATE_90_LEFT, IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP, IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP, IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP), IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90, IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP), IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP), IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP), }; /* 90-degree rotations require the IRT unit */ #define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0) enum ipu_color_space { IPUV3_COLORSPACE_RGB, IPUV3_COLORSPACE_YUV, Loading