Commit 8b83369d authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V updates from Palmer Dabbelt:
 "A handful of new RISC-V related patches for this merge window:

   - A check to ensure drivers are properly using uaccess. This isn't
     manifesting with any of the drivers I'm currently using, but may
     catch errors in new drivers.

   - Some preliminary support for the FU740, along with the HiFive
     Unleashed it will appear on.

   - NUMA support for RISC-V, which involves making the arm64 code
     generic.

   - Support for kasan on the vmalloc region.

   - A handful of new drivers for the Kendryte K210, along with the DT
     plumbing required to boot on a handful of K210-based boards.

   - Support for allocating ASIDs.

   - Preliminary support for kernels larger than 128MiB.

   - Various other improvements to our KASAN support, including the
     utilization of huge pages when allocating the KASAN regions.

  We may have already found a bug with the KASAN_VMALLOC code, but it's
  passing my tests. There's a fix in the works, but that will probably
  miss the merge window.

* tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (75 commits)
  riscv: Improve kasan population by using hugepages when possible
  riscv: Improve kasan population function
  riscv: Use KASAN_SHADOW_INIT define for kasan memory initialization
  riscv: Improve kasan definitions
  riscv: Get rid of MAX_EARLY_MAPPING_SIZE
  soc: canaan: Sort the Makefile alphabetically
  riscv: Disable KSAN_SANITIZE for vDSO
  riscv: Remove unnecessary declaration
  riscv: Add Canaan Kendryte K210 SD card defconfig
  riscv: Update Canaan Kendryte K210 defconfig
  riscv: Add Kendryte KD233 board device tree
  riscv: Add SiPeed MAIXDUINO board device tree
  riscv: Add SiPeed MAIX GO board device tree
  riscv: Add SiPeed MAIX DOCK board device tree
  riscv: Add SiPeed MAIX BiT board device tree
  riscv: Update Canaan Kendryte K210 device tree
  dt-bindings: add resets property to dw-apb-timer
  dt-bindings: fix sifive gpio properties
  dt-bindings: update sifive uart compatible string
  dt-bindings: update sifive clint compatible string
  ...
parents 8f47d753 d7fbcf40
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+25 −4
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@@ -13,7 +13,10 @@ maintainers:
properties:
  compatible:
    items:
      - const: sifive,fu540-c000-gpio
      - enum:
          - sifive,fu540-c000-gpio
          - sifive,fu740-c000-gpio
          - canaan,k210-gpiohs
      - const: sifive,gpio0

  reg:
@@ -21,9 +24,9 @@ properties:

  interrupts:
    description:
      interrupt mapping one per GPIO. Maximum 16 GPIOs.
      Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
    minItems: 1
    maxItems: 16
    maxItems: 32

  interrupt-controller: true

@@ -36,6 +39,14 @@ properties:
  "#gpio-cells":
    const: 2

  ngpios:
    description:
      The number of GPIOs available on the controller implementation.
      It is 16 for the SiFive SoCs and 32 for the Canaan K210.
    minimum: 1
    maximum: 32
    default: 16

  gpio-controller: true

required:
@@ -44,10 +55,20 @@ required:
  - interrupts
  - interrupt-controller
  - "#interrupt-cells"
  - clocks
  - "#gpio-cells"
  - gpio-controller

if:
  properties:
    compatible:
      contains:
        enum:
          - sifive,fu540-c000-gpio
          - sifive,fu740-c000-gpio
then:
  required:
    - clocks

additionalProperties: false

examples:
+8 −5
Original line number Diff line number Diff line
@@ -8,10 +8,11 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive Platform-Level Interrupt Controller (PLIC)

description:
  SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
  (PLIC) high-level specification in the RISC-V Privileged Architecture
  specification. The PLIC connects all external interrupts in the system to all
  hart contexts in the system, via the external interrupt source in each hart.
  SiFive SoCs and other RISC-V SoCs include an implementation of the
  Platform-Level Interrupt Controller (PLIC) high-level specification in
  the RISC-V Privileged Architecture specification. The PLIC connects all
  external interrupts in the system to all hart contexts in the system, via
  the external interrupt source in each hart.

  A hart context is a privilege mode in a hardware execution thread. For example,
  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
@@ -42,7 +43,9 @@ maintainers:
properties:
  compatible:
    items:
      - const: sifive,fu540-c000-plic
      - enum:
          - sifive,fu540-c000-plic
          - canaan,k210-plic
      - const: sifive,plic-1.0.0

  reg:
+109 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/canaan,k210-sysctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Canaan Kendryte K210 System Controller Device Tree Bindings

maintainers:
  - Damien Le Moal <damien.lemoal@wdc.com>

description:
  Canaan Inc. Kendryte K210 SoC system controller which provides a
  register map for controlling the clocks, reset signals and pin power
  domains of the SoC.

properties:
  compatible:
    items:
      - const: canaan,k210-sysctl
      - const: syscon
      - const: simple-mfd

  clocks:
    maxItems: 1
    description:
      System controller Advanced Power Bus (APB) interface clock source.

  clock-names:
    items:
      - const: pclk

  reg:
    maxItems: 1

  clock-controller:
    # Child node
    type: object
    $ref: "../clock/canaan,k210-clk.yaml"
    description:
      Clock controller for the SoC clocks. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/clock/canaan,k210-clk.yaml.

  reset-controller:
    # Child node
    type: object
    $ref: "../reset/canaan,k210-rst.yaml"
    description:
      Reset controller for the SoC. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/reset/canaan,k210-rst.yaml.

  syscon-reboot:
    # Child node
    type: object
    $ref: "../power/reset/syscon-reboot.yaml"
    description:
      Reboot method for the SoC. This child node definition
      should follow the bindings specified in
      Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml.

required:
  - compatible
  - clocks
  - reg
  - clock-controller

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/k210-clk.h>
    #include <dt-bindings/reset/k210-rst.h>

    clocks {
      in0: oscllator {
        compatible = "fixed-clock";
        #clock-cells = <0>;
        clock-frequency = <26000000>;
      };
    };

    sysctl: syscon@50440000 {
      compatible = "canaan,k210-sysctl",
                   "syscon", "simple-mfd";
      reg = <0x50440000 0x100>;
      clocks = <&sysclk K210_CLK_APB1>;
      clock-names = "pclk";

      sysclk: clock-controller {
        #clock-cells = <1>;
        compatible = "canaan,k210-clk";
        clocks = <&in0>;
      };

      sysrst: reset-controller {
        compatible = "canaan,k210-rst";
        #reset-cells = <1>;
      };

      reboot: syscon-reboot {
        compatible = "syscon-reboot";
        regmap = <&sysctl>;
        offset = <48>;
        mask = <1>;
        value = <1>;
      };
    };
+171 −0
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/canaan,k210-fpioa.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Canaan Kendryte K210 FPIOA Device Tree Bindings

maintainers:
  - Damien Le Moal <damien.lemoal@wdc.com>

description:
  The Canaan Kendryte K210 SoC Fully Programmable IO Array (FPIOA)
  controller allows assiging any of 256 possible functions to any of
  48 IO pins of the SoC. Pin function configuration is performed on
  a per-pin basis.

properties:
  compatible:
    const: canaan,k210-fpioa

  reg:
    maxItems: 1
    description:
      Address and length of the register set for the FPIOA controller.

  clocks:
    items:
      - description: Controller reference clock source
      - description: APB interface clock source

  clock-names:
    items:
      - const: ref
      - const: pclk

  resets:
    maxItems: 1

  canaan,k210-sysctl-power:
    $ref: /schemas/types.yaml#/definitions/phandle-array
    description: |
      phandle of the K210 system controller node and offset of its
      power domain control register.

patternProperties:
  '-pinmux$':
    type: object
    $ref: /schemas/pinctrl/pinmux-node.yaml
    description:
      FPIOA client devices use sub-nodes to define the desired pin
      configuration. Client device sub-nodes use the pinux property
      below.

    properties:
      pinmux:
        description:
          List of IO pins alternate functions. The values for each IO
          pin is a combination of an IO pin number (0 to 47) with the
          desired function for the IO pin. Functions are defined as
          macros in include/dt-bindings/pinctrl/k210-fpioa.h.
          The K210_FPIOA(IO pin, function) macro is provided to
          facilitate the combination of IO pin numbers and functions.

    required:
      - pinmux

    additionalProperties: false

  '-pins$':
    type: object
    $ref: /schemas/pinctrl/pincfg-node.yaml
    description:
      FPIOA client devices use sub-nodes to define the desired
      configuration of pins. Client device sub-nodes use the
      properties below.

    properties:
      pins:
        description:
          List of IO pins affected by the properties specified in this
          subnode. IO pins are identified using the pin names "IO_xx".
          Pin configuration nodes can also define the power domain to
          be used for the SoC pin groups A0 (IO pins 0-5),
          A1 (IO pins 6-11), A2 (IO pins 12-17), B0 (IO pins 18-23),
          B1 (IO pins 24-29), B2 (IO pins 30-35), B3 (IO pins 30-35),
          C0 (IO pins 36-41) and C1 (IO pins 42-47) using the
          power-source property.
        items:
          anyOf:
            - pattern: "^(IO_([0-9]*))|(A[0-2])|(B[3-5])|(C[6-7])$"
            - enum: [ IO_0, IO_1, IO_2, IO_3, IO_4, IO_5, IO_6, IO_7,
                      IO_8, IO_9, IO_10, IO_11, IO_12, IO_13, IO_14,
                      IO_15, IO_16, IO_17, IO_18, IO_19, IO_20, IO_21,
                      IO_22, IO_23, IO_24, IO_25, IO_26, IO_27, IO_28,
                      IO_29, IO_30, IO_31, IO_32, IO_33, IO_34, IO_35,
                      IO_36, IO_37, IO_38, IO_39, IO_40, IO_41, IO_42,
                      IO_43, IO_44, IO_45, IO_46, IO_47,
                      A0, A1, A2, B3, B4, B5, C6, C7 ]
      bias-disable: true

      bias-pull-down: true

      bias-pull-up: true

      drive-strength: true

      drive-strength-microamp: true

      input-enable: true

      input-disable: true

      input-schmitt-enable: true

      input-schmitt-disable: true

      input-polarity-invert:
        description:
          Enable or disable pin input polarity inversion.

      output-enable: true

      output-disable: true

      output-high: true

      output-low: true

      output-polarity-invert:
        description:
          Enable or disable pin output polarity inversion.

      slew-rate: true

      power-source: true

    additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - canaan,k210-sysctl-power

additionalProperties: false

examples:
  - |
    #include <dt-bindings/pinctrl/k210-fpioa.h>
    #include <dt-bindings/clock/k210-clk.h>
    #include <dt-bindings/reset/k210-rst.h>

    fpioa: pinmux@502B0000 {
      compatible = "canaan,k210-fpioa";
      reg = <0x502B0000 0x100>;
      clocks = <&sysclk K210_CLK_FPIOA>,
               <&sysclk K210_CLK_APB0>;
      clock-names = "ref", "pclk";
      resets = <&sysrst K210_RST_FPIOA>;
      canaan,k210-sysctl-power = <&sysctl 108>;
      pinctrl-0 = <&jtag_pinctrl>;
      pinctrl-names = "default";

      jtag_pinctrl: jtag-pinmux {
        pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>,
                 <K210_FPIOA(1, K210_PCF_JTAG_TDI)>,
                 <K210_FPIOA(2, K210_PCF_JTAG_TMS)>,
                 <K210_FPIOA(3, K210_PCF_JTAG_TDO)>;
      };
    };
+6 −3
Original line number Diff line number Diff line
@@ -25,12 +25,15 @@ description:
properties:
  compatible:
    items:
      - const: sifive,fu540-c000-pwm
      - enum:
          - sifive,fu540-c000-pwm
          - sifive,fu740-c000-pwm
      - const: sifive,pwm0
    description:
      Should be "sifive,<chip>-pwm" and "sifive,pwm<version>". Supported
      compatible strings are "sifive,fu540-c000-pwm" for the SiFive PWM v0
      as integrated onto the SiFive FU540 chip, and "sifive,pwm0" for the
      compatible strings are "sifive,fu540-c000-pwm" and
      "sifive,fu740-c000-pwm" for the SiFive PWM v0 as integrated onto the
      SiFive FU540 and FU740 chip respectively, and "sifive,pwm0" for the
      SiFive PWM v0 IP block with no chip integration tweaks.
      Please refer to sifive-blocks-ip-versioning.txt for details.

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