Commit 8b6f6877 authored by Borislav Petkov (AMD)'s avatar Borislav Petkov (AMD)
Browse files

x86/cpu/amd: Move the errata checking functionality up 



Avoid new and remove old forward declarations.

No functional changes.

Signed-off-by: default avatarBorislav Petkov (AMD) <bp@alien8.de>
parent fdf0eaf1

arch/x86/kernel/cpu/amd.c

+67 −72
Original line number Diff line number Diff line
@@ -27,11 +27,6 @@ 


#include "cpu.h"



static const int amd_erratum_383[];

static const int amd_erratum_400[];

static const int amd_erratum_1054[];

static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);



/*

 * nodes_per_socket: Stores the number of nodes per socket.

 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
@@ -39,6 +34,73 @@ static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 
 */

static u32 nodes_per_socket = 1;



/*

 * AMD errata checking

 *

 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or

 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that

 * have an OSVW id assigned, which it takes as first argument. Both take a

 * variable number of family-specific model-stepping ranges created by

 * AMD_MODEL_RANGE().

 *

 * Example:

 *

 * const int amd_erratum_319[] =

 *	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),

 *			   AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),

 *			   AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));

 */



#define AMD_LEGACY_ERRATUM(...)		{ -1, __VA_ARGS__, 0 }

#define AMD_OSVW_ERRATUM(osvw_id, ...)	{ osvw_id, __VA_ARGS__, 0 }

#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \

	((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))

#define AMD_MODEL_RANGE_FAMILY(range)	(((range) >> 24) & 0xff)

#define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)

#define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)



static const int amd_erratum_400[] =

	AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),

			    AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));



static const int amd_erratum_383[] =

	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));



/* #1054: Instructions Retired Performance Counter May Be Inaccurate */

static const int amd_erratum_1054[] =

	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));



static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)

{

	int osvw_id = *erratum++;

	u32 range;

	u32 ms;



	if (osvw_id >= 0 && osvw_id < 65536 &&

	    cpu_has(cpu, X86_FEATURE_OSVW)) {

		u64 osvw_len;



		rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);

		if (osvw_id < osvw_len) {

			u64 osvw_bits;



			rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),

			    osvw_bits);

			return osvw_bits & (1ULL << (osvw_id & 0x3f));

		}

	}



	/* OSVW unavailable or ID unknown, match family-model-stepping range */

	ms = (cpu->x86_model << 4) | cpu->x86_stepping;

	while ((range = *erratum++))

		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&

		    (ms >= AMD_MODEL_RANGE_START(range)) &&

		    (ms <= AMD_MODEL_RANGE_END(range)))

			return true;



	return false;

}



static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)

{

	u32 gprs[8] = { 0 };
@@ -1115,73 +1177,6 @@ static const struct cpu_dev amd_cpu_dev = { 


cpu_dev_register(amd_cpu_dev);



/*

 * AMD errata checking

 *

 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or

 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that

 * have an OSVW id assigned, which it takes as first argument. Both take a

 * variable number of family-specific model-stepping ranges created by

 * AMD_MODEL_RANGE().

 *

 * Example:

 *

 * const int amd_erratum_319[] =

 *	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),

 *			   AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),

 *			   AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));

 */



#define AMD_LEGACY_ERRATUM(...)		{ -1, __VA_ARGS__, 0 }

#define AMD_OSVW_ERRATUM(osvw_id, ...)	{ osvw_id, __VA_ARGS__, 0 }

#define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \

	((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))

#define AMD_MODEL_RANGE_FAMILY(range)	(((range) >> 24) & 0xff)

#define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)

#define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)



static const int amd_erratum_400[] =

	AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),

			    AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));



static const int amd_erratum_383[] =

	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));



/* #1054: Instructions Retired Performance Counter May Be Inaccurate */

static const int amd_erratum_1054[] =

	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf));



static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)

{

	int osvw_id = *erratum++;

	u32 range;

	u32 ms;



	if (osvw_id >= 0 && osvw_id < 65536 &&

	    cpu_has(cpu, X86_FEATURE_OSVW)) {

		u64 osvw_len;



		rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);

		if (osvw_id < osvw_len) {

			u64 osvw_bits;



			rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),

			    osvw_bits);

			return osvw_bits & (1ULL << (osvw_id & 0x3f));

		}

	}



	/* OSVW unavailable or ID unknown, match family-model-stepping range */

	ms = (cpu->x86_model << 4) | cpu->x86_stepping;

	while ((range = *erratum++))

		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&

		    (ms >= AMD_MODEL_RANGE_START(range)) &&

		    (ms <= AMD_MODEL_RANGE_END(range)))

			return true;



	return false;

}



static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask);



static unsigned int amd_msr_dr_addr_masks[] = {