Commit 8b6bdd71 authored by Mathias Nyman's avatar Mathias Nyman Committed by Yongqiang Liu
Browse files

xhci: Fix 5.12 regression of missing xHC cache clearing command after a Stall 

mainline inclusion
from mainline-v5.13-rc4
commit a7f2e927
category: bugfix
bugzilla: https://gitee.com/src-openeuler/kernel/issues/IACV8P
CVE: CVE-2024-40927

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=a7f2e9272aff1ccfe0fc801dab1d5a7a1c6b7ed2



--------------------------------

If endpoints halts due to a stall then the dequeue pointer read from
hardware may already be set ahead of the stalled TRB.
After commit 674f8438 ("xhci: split handling halted endpoints into two
steps") in 5.12 xhci driver won't issue a Set TR Dequeue if hardware
dequeue pointer is already in the right place.

Turns out the "Set TR Dequeue pointer" command is anyway needed as it in
addition to moving the dequeue pointer also clears endpoint state and
cache.

Fixes: 674f8438 ("xhci: split handling halted endpoints into two steps")
Cc: <stable@vger.kernel.org> # 5.12
Reported-by: default avatarPeter Ganzhorn <peter.ganzhorn@googlemail.com>
Tested-by: default avatarPeter Ganzhorn <peter.ganzhorn@googlemail.com>
Signed-off-by: default avatarMathias Nyman <mathias.nyman@linux.intel.com>
Link: https://lore.kernel.org/r/20210525074100.1154090-3-mathias.nyman@linux.intel.com


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: default avatarYongqiang Liu <liuyongqiang13@huawei.com>
parent 370e2d20

drivers/usb/host/xhci-ring.c

+6 −2
Original line number Diff line number Diff line
@@ -929,14 +929,18 @@ static int xhci_invalidate_cancelled_tds(struct xhci_virt_ep *ep) 
			continue;

		}

		/*

		 * If ring stopped on the TD we need to cancel, then we have to

		 * If a ring stopped on the TD we need to cancel then we have to

		 * move the xHC endpoint ring dequeue pointer past this TD.

		 * Rings halted due to STALL may show hw_deq is past the stalled

		 * TD, but still require a set TR Deq command to flush xHC cache.

		 */

		hw_deq = xhci_get_hw_deq(xhci, ep->vdev, ep->ep_index,

					 td->urb->stream_id);

		hw_deq &= ~0xf;



		if (trb_in_td(xhci, td->start_seg, td->first_trb,

		if (td->cancel_status == TD_HALTED) {

			cached_td = td;

		} else if (trb_in_td(xhci, td->start_seg, td->first_trb,

			      td->last_trb, hw_deq, false)) {

			switch (td->cancel_status) {

			case TD_CLEARED: /* TD is already no-op */