Commit 8b46cc65 authored by Anshuman Gupta's avatar Anshuman Gupta
Browse files

drm/i915: Tweaked Wa_14010685332 for all PCHs 



dispcnlunit1_cp_xosc_clkreq clock observed to be active on TGL-H platform
despite Wa_14010685332 original sequence,
thus blocks entry to deeper s0ix state.

The Tweaked Wa_14010685332 sequence fixes this issue, therefore use tweaked
Wa_14010685332 sequence for every PCH since PCH_CNP.

v2:
- removed RKL from comment and simplified condition. [Rodrigo]

Fixes: b896898c ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11 platforms")
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: default avatarAnshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210810113112.31739-2-anshuman.gupta@intel.com
parent c5589bb5

drivers/gpu/drm/i915/display/intel_display_power.c

+8 −8
Original line number Diff line number Diff line
@@ -6329,13 +6329,13 @@ void intel_display_power_suspend_late(struct drm_i915_private *i915) 
	if (DISPLAY_VER(i915) >= 11 || IS_GEMINILAKE(i915) ||

	    IS_BROXTON(i915)) {

		bxt_enable_dc9(i915);

		/* Tweaked Wa_14010685332:icp,jsp,mcc */

		if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)

			intel_de_rmw(i915, SOUTH_CHICKEN1,

				     SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);

	} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {

		hsw_enable_pc8(i915);

	}



	/* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */

	if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)

		intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);

}



void intel_display_power_resume_early(struct drm_i915_private *i915)
@@ -6344,13 +6344,13 @@ void intel_display_power_resume_early(struct drm_i915_private *i915) 
	    IS_BROXTON(i915)) {

		gen9_sanitize_dc_state(i915);

		bxt_disable_dc9(i915);

		/* Tweaked Wa_14010685332:icp,jsp,mcc */

		if (INTEL_PCH_TYPE(i915) >= PCH_ICP && INTEL_PCH_TYPE(i915) <= PCH_MCC)

			intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);



	} else if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {

		hsw_disable_pc8(i915);

	}



	/* Tweaked Wa_14010685332:cnp,icp,jsp,mcc,tgp,adp */

	if (INTEL_PCH_TYPE(i915) >= PCH_CNP && INTEL_PCH_TYPE(i915) < PCH_DG1)

		intel_de_rmw(i915, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);

}



void intel_display_power_suspend(struct drm_i915_private *i915)

drivers/gpu/drm/i915/i915_irq.c

+0 −21
Original line number Diff line number Diff line
@@ -3079,24 +3079,6 @@ static void valleyview_irq_reset(struct drm_i915_private *dev_priv) 
	spin_unlock_irq(&dev_priv->irq_lock);

}



static void cnp_display_clock_wa(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;



	/*

	 * Wa_14010685332:cnp/cmp,tgp,adp

	 * TODO: Clarify which platforms this applies to

	 * TODO: Figure out if this workaround can be applied in the s0ix suspend/resume handlers as

	 * on earlier platforms and whether the workaround is also needed for runtime suspend/resume

	 */

	if (INTEL_PCH_TYPE(dev_priv) == PCH_CNP ||

	    (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && INTEL_PCH_TYPE(dev_priv) < PCH_DG1)) {

		intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS,

				 SBCLK_RUN_REFCLK_DIS);

		intel_uncore_rmw(uncore, SOUTH_CHICKEN1, SBCLK_RUN_REFCLK_DIS, 0);

	}

}



static void gen8_display_irq_reset(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;
@@ -3130,7 +3112,6 @@ static void gen8_irq_reset(struct drm_i915_private *dev_priv) 
	if (HAS_PCH_SPLIT(dev_priv))

		ibx_irq_reset(dev_priv);



	cnp_display_clock_wa(dev_priv);

}



static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
@@ -3174,8 +3155,6 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv) 


	if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)

		GEN3_IRQ_RESET(uncore, SDE);



	cnp_display_clock_wa(dev_priv);

}



static void gen11_irq_reset(struct drm_i915_private *dev_priv)