Commit 8b406fd4 authored by Niklas Söderlund's avatar Niklas Söderlund Committed by Geert Uytterhoeven
Browse files

clk: renesas: r8a779g0: Add CSI-2 clocks 



Add the CSI core clock and the CSI40 and CSI41 module clocks, which are
used by the CSI-2 Interfaces on the Renesas R-Car V4H (R8A779G0) SoC.

Signed-off-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230211143655.3809756-2-niklas.soderlund+renesas@ragnatech.se


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 7502a04d

drivers/clk/renesas/r8a779g0-cpg-mssr.c

+3 −0
Original line number Diff line number Diff line
@@ -146,6 +146,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = { 
	DEF_FIXED("vcbus",	R8A779G0_CLK_VCBUS,	CLK_VC,		1, 1),

	DEF_FIXED("vcbusd2",	R8A779G0_CLK_VCBUSD2,	CLK_VC,		2, 1),

	DEF_DIV6P1("canfd",     R8A779G0_CLK_CANFD,	CLK_PLL5_DIV4,	0x878),

	DEF_DIV6P1("csi",	R8A779G0_CLK_CSI,	CLK_PLL5_DIV4,	0x880),

	DEF_FIXED("dsiref",	R8A779G0_CLK_DSIREF,	CLK_PLL5_DIV4,	48, 1),

	DEF_DIV6P1("dsiext",	R8A779G0_CLK_DSIEXT,	CLK_PLL5_DIV4,	0x884),
@@ -165,6 +166,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = { 
	DEF_MOD("avb1",		212,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("avb2",		213,	R8A779G0_CLK_S0D4_HSC),

	DEF_MOD("canfd0",	328,	R8A779G0_CLK_SASYNCPERD2),

	DEF_MOD("csi40",	331,	R8A779G0_CLK_CSI),

	DEF_MOD("csi41",	400,	R8A779G0_CLK_CSI),

	DEF_MOD("dis0",		411,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("dsitxlink0",	415,	R8A779G0_CLK_VIOBUSD2),

	DEF_MOD("dsitxlink1",	416,	R8A779G0_CLK_VIOBUSD2),