Commit 8b12a62a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2021-03-19' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Regular fixes pull, pretty small set of fixes, a couple of i915 and
  amdgpu, one ttm, one nouveau and one omap. Probably smaller than usual
  for this time, so we'll see if something pops up next week or if this
  will continue to stay small.

  Summary:

  ttm:
   - Make ttm_bo_unpin() not wraparound on too many unpins

  omap:
   - Fix coccicheck warning in omap

  amdgpu:
   - DCN 3.0 gamma fixes
   - DCN 2.1 corrupt screen fix

  i915:
   - Workaround async flip + VT-d frame corruption on HSW/BDW
   - Fix NMI watchdog crash due to uninitialized OA buffer use on gen12+

  nouveau:
   - workaround oops with bo syncing"

* tag 'drm-fixes-2021-03-19' of git://anongit.freedesktop.org/drm/drm:
  nouveau: Skip unvailable ttm page entries
  drm/amd/display: Remove MPC gamut remap logic for DCN30
  drm/amd/display: Correct algorithm for reversed gamma
  drm/omap: dsi: fix unsigned expression compared with zero
  i915/perf: Start hrtimer only if sampling the OA buffer
  drm/i915: Workaround async flip + VT-d corruption on HSW/BDW
  drm/amd/display: Copy over soc values before bounding box creation
  drm/ttm: make ttm_bo_unpin more defensive
parents 81aa0968 e94c55b8

drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

+2 −32
Original line number Diff line number Diff line
@@ -1507,36 +1507,6 @@ static void dcn20_update_dchubp_dpp( 
	if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed

			|| pipe_ctx->stream->update_flags.bits.gamut_remap

			|| pipe_ctx->stream->update_flags.bits.out_csc) {

		struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;



		if (mpc->funcs->set_gamut_remap) {

			int i;

			int mpcc_id = hubp->inst;

			struct mpc_grph_gamut_adjustment adjust;

			bool enable_remap_dpp = false;



			memset(&adjust, 0, sizeof(adjust));

			adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;



			/* save the enablement of gamut remap for dpp */

			enable_remap_dpp = pipe_ctx->stream->gamut_remap_matrix.enable_remap;



			/* force bypass gamut remap for dpp/cm */

			pipe_ctx->stream->gamut_remap_matrix.enable_remap = false;

			dc->hwss.program_gamut_remap(pipe_ctx);



			/* restore gamut remap flag and use this remap into mpc */

			pipe_ctx->stream->gamut_remap_matrix.enable_remap = enable_remap_dpp;



			/* build remap matrix for top plane if enabled */

			if (enable_remap_dpp && pipe_ctx->top_pipe == NULL) {

					adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;

					for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)

						adjust.temperature_matrix[i] =

								pipe_ctx->stream->gamut_remap_matrix.matrix[i];

			}

			mpc->funcs->set_gamut_remap(mpc, mpcc_id, &adjust);

		} else

		/* dpp/cm gamut remap*/

		dc->hwss.program_gamut_remap(pipe_ctx);

drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

+5 −0
Original line number Diff line number Diff line
@@ -1595,6 +1595,11 @@ static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_param 
	dcn2_1_soc.num_chans = bw_params->num_channels;



	ASSERT(clk_table->num_entries);

	/* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */

	for (i = 0; i < dcn2_1_soc.num_states + 1; i++) {

		clock_limits[i] = dcn2_1_soc.clock_limits[i];

	}



	for (i = 0; i < clk_table->num_entries; i++) {

		/* loop backwards*/

		for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {

drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c

+18 −8
Original line number Diff line number Diff line
@@ -113,6 +113,7 @@ bool cm3_helper_translate_curve_to_hw_format( 
	struct pwl_result_data *rgb_resulted;

	struct pwl_result_data *rgb;

	struct pwl_result_data *rgb_plus_1;

	struct pwl_result_data *rgb_minus_1;

	struct fixed31_32 end_value;



	int32_t region_start, region_end;
@@ -140,7 +141,7 @@ bool cm3_helper_translate_curve_to_hw_format( 
		region_start = -MAX_LOW_POINT;

		region_end   = NUMBER_REGIONS - MAX_LOW_POINT;

	} else {

		/* 10 segments

		/* 11 segments

		 * segment is from 2^-10 to 2^0

		 * There are less than 256 points, for optimization

		 */
@@ -154,9 +155,10 @@ bool cm3_helper_translate_curve_to_hw_format( 
		seg_distr[7] = 4;

		seg_distr[8] = 4;

		seg_distr[9] = 4;

		seg_distr[10] = 1;



		region_start = -10;

		region_end = 0;

		region_end = 1;

	}



	for (i = region_end - region_start; i < MAX_REGIONS_NUMBER ; i++)
@@ -189,6 +191,10 @@ bool cm3_helper_translate_curve_to_hw_format( 
	rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];

	rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];



	rgb_resulted[hw_points].red = rgb_resulted[hw_points - 1].red;

	rgb_resulted[hw_points].green = rgb_resulted[hw_points - 1].green;

	rgb_resulted[hw_points].blue = rgb_resulted[hw_points - 1].blue;



	// All 3 color channels have same x

	corner_points[0].red.x = dc_fixpt_pow(dc_fixpt_from_int(2),

					     dc_fixpt_from_int(region_start));
@@ -259,15 +265,18 @@ bool cm3_helper_translate_curve_to_hw_format( 


	rgb = rgb_resulted;

	rgb_plus_1 = rgb_resulted + 1;

	rgb_minus_1 = rgb;



	i = 1;

	while (i != hw_points + 1) {

		if (i >= hw_points - 1) {

			if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))

			rgb_plus_1->red = rgb->red;

				rgb_plus_1->red = dc_fixpt_add(rgb->red, rgb_minus_1->delta_red);

			if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))

			rgb_plus_1->green = rgb->green;

				rgb_plus_1->green = dc_fixpt_add(rgb->green, rgb_minus_1->delta_green);

			if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))

			rgb_plus_1->blue = rgb->blue;

				rgb_plus_1->blue = dc_fixpt_add(rgb->blue, rgb_minus_1->delta_blue);

		}



		rgb->delta_red   = dc_fixpt_sub(rgb_plus_1->red,   rgb->red);

		rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
@@ -283,6 +292,7 @@ bool cm3_helper_translate_curve_to_hw_format( 
		}



		++rgb_plus_1;

		rgb_minus_1 = rgb;

		++rgb;

		++i;

	}

drivers/gpu/drm/i915/i915_perf.c

+5 −8
Original line number Diff line number Diff line
@@ -603,7 +603,6 @@ static int append_oa_sample(struct i915_perf_stream *stream, 
{

	int report_size = stream->oa_buffer.format_size;

	struct drm_i915_perf_record_header header;

	u32 sample_flags = stream->sample_flags;



	header.type = DRM_I915_PERF_RECORD_SAMPLE;

	header.pad = 0;
@@ -617,10 +616,8 @@ static int append_oa_sample(struct i915_perf_stream *stream, 
		return -EFAULT;

	buf += sizeof(header);



	if (sample_flags & SAMPLE_OA_REPORT) {

	if (copy_to_user(buf, report, report_size))

		return -EFAULT;

	}



	(*offset) += header.size;
@@ -2682,7 +2679,7 @@ static void i915_oa_stream_enable(struct i915_perf_stream *stream) 


	stream->perf->ops.oa_enable(stream);



	if (stream->periodic)

	if (stream->sample_flags & SAMPLE_OA_REPORT)

		hrtimer_start(&stream->poll_check_timer,

			      ns_to_ktime(stream->poll_oa_period),

			      HRTIMER_MODE_REL_PINNED);
@@ -2745,7 +2742,7 @@ static void i915_oa_stream_disable(struct i915_perf_stream *stream) 
{

	stream->perf->ops.oa_disable(stream);



	if (stream->periodic)

	if (stream->sample_flags & SAMPLE_OA_REPORT)

		hrtimer_cancel(&stream->poll_check_timer);

}
@@ -3028,7 +3025,7 @@ static ssize_t i915_perf_read(struct file *file, 
	 * disabled stream as an error. In particular it might otherwise lead

	 * to a deadlock for blocking file descriptors...

	 */

	if (!stream->enabled)

	if (!stream->enabled || !(stream->sample_flags & SAMPLE_OA_REPORT))

		return -EIO;



	if (!(file->f_flags & O_NONBLOCK)) {

drivers/gpu/drm/i915/i915_reg.h

+22 −1
Original line number Diff line number Diff line
@@ -3316,7 +3316,18 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 


#define ILK_DISPLAY_CHICKEN1	_MMIO(0x42000)

#define   ILK_FBCQ_DIS		(1 << 22)

#define	  ILK_PABSTRETCH_DIS	(1 << 21)

#define   ILK_PABSTRETCH_DIS	REG_BIT(21)

#define   ILK_SABSTRETCH_DIS	REG_BIT(20)

#define   IVB_PRI_STRETCH_MAX_MASK	REG_GENMASK(21, 20)

#define   IVB_PRI_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 0)

#define   IVB_PRI_STRETCH_MAX_X4	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 1)

#define   IVB_PRI_STRETCH_MAX_X2	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 2)

#define   IVB_PRI_STRETCH_MAX_X1	REG_FIELD_PREP(IVB_PRI_STRETCH_MAX_MASK, 3)

#define   IVB_SPR_STRETCH_MAX_MASK	REG_GENMASK(19, 18)

#define   IVB_SPR_STRETCH_MAX_X8	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 0)

#define   IVB_SPR_STRETCH_MAX_X4	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 1)

#define   IVB_SPR_STRETCH_MAX_X2	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2)

#define   IVB_SPR_STRETCH_MAX_X1	REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3)





/*
@@ -8039,6 +8050,16 @@ enum { 


#define _CHICKEN_PIPESL_1_A	0x420b0

#define _CHICKEN_PIPESL_1_B	0x420b4

#define  HSW_PRI_STRETCH_MAX_MASK	REG_GENMASK(28, 27)

#define  HSW_PRI_STRETCH_MAX_X8		REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)

#define  HSW_PRI_STRETCH_MAX_X4		REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)

#define  HSW_PRI_STRETCH_MAX_X2		REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)

#define  HSW_PRI_STRETCH_MAX_X1		REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)

#define  HSW_SPR_STRETCH_MAX_MASK	REG_GENMASK(26, 25)

#define  HSW_SPR_STRETCH_MAX_X8		REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)

#define  HSW_SPR_STRETCH_MAX_X4		REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)

#define  HSW_SPR_STRETCH_MAX_X2		REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)

#define  HSW_SPR_STRETCH_MAX_X1		REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)

#define  HSW_FBCQ_DIS			(1 << 22)

#define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)

#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)