Loading drivers/spi/spi-dw-dma.c +13 −1 Original line number Diff line number Diff line Loading @@ -372,8 +372,20 @@ static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer) { u16 imr = 0, dma_ctrl = 0; /* * Having a Rx DMA channel serviced with higher priority than a Tx DMA * channel might not be enough to provide a well balanced DMA-based * SPI transfer interface. There might still be moments when the Tx DMA * channel is occasionally handled faster than the Rx DMA channel. * That in its turn will eventually cause the SPI Rx FIFO overflow if * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's * cleared by the Rx DMA channel. In order to fix the problem the Tx * DMA activity is intentionally slowed down by limiting the SPI Tx * FIFO depth with a value twice bigger than the Tx burst length * calculated earlier by the dw_spi_dma_maxburst_init() method. */ dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - dws->txburst); dw_writel(dws, DW_SPI_DMATDLR, dws->txburst); if (xfer->tx_buf) dma_ctrl |= SPI_DMA_TDMAE; Loading Loading
drivers/spi/spi-dw-dma.c +13 −1 Original line number Diff line number Diff line Loading @@ -372,8 +372,20 @@ static int dw_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer) { u16 imr = 0, dma_ctrl = 0; /* * Having a Rx DMA channel serviced with higher priority than a Tx DMA * channel might not be enough to provide a well balanced DMA-based * SPI transfer interface. There might still be moments when the Tx DMA * channel is occasionally handled faster than the Rx DMA channel. * That in its turn will eventually cause the SPI Rx FIFO overflow if * SPI bus speed is high enough to fill the SPI Rx FIFO in before it's * cleared by the Rx DMA channel. In order to fix the problem the Tx * DMA activity is intentionally slowed down by limiting the SPI Tx * FIFO depth with a value twice bigger than the Tx burst length * calculated earlier by the dw_spi_dma_maxburst_init() method. */ dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1); dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - dws->txburst); dw_writel(dws, DW_SPI_DMATDLR, dws->txburst); if (xfer->tx_buf) dma_ctrl |= SPI_DMA_TDMAE; Loading