Commit 8a8ca83e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'perf-core-2020-12-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf updates from Thomas Gleixner:
 "Core:

   - Better handling of page table leaves on archictectures which have
     architectures have non-pagetable aligned huge/large pages. For such
     architectures a leaf can actually be part of a larger entry.

   - Prevent a deadlock vs exec_update_mutex

  Architectures:

   - The related updates for page size calculation of leaf entries

   - The usual churn to support new CPUs

   - Small fixes and improvements all over the place"

* tag 'perf-core-2020-12-14' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (24 commits)
  perf/x86/intel: Add Tremont Topdown support
  uprobes/x86: Fix fall-through warnings for Clang
  perf/x86: Fix fall-through warnings for Clang
  kprobes/x86: Fix fall-through warnings for Clang
  perf/x86/intel/lbr: Fix the return type of get_lbr_cycles()
  perf/x86/intel: Fix rtm_abort_event encoding on Ice Lake
  x86/kprobes: Restore BTF if the single-stepping is cancelled
  perf: Break deadlock involving exec_update_mutex
  sparc64/mm: Implement pXX_leaf_size() support
  powerpc/8xx: Implement pXX_leaf_size() support
  arm64/mm: Implement pXX_leaf_size() support
  perf/core: Fix arch_perf_get_page_size()
  mm: Introduce pXX_leaf_size()
  mm/gup: Provide gup_get_pte() more generic
  perf/x86/intel: Add event constraint for CYCLE_ACTIVITY.STALLS_MEM_ANY
  perf/x86/intel/uncore: Add Rocket Lake support
  perf/x86/msr: Add Rocket Lake CPU support
  perf/x86/cstate: Add Rocket Lake CPU support
  perf/x86/intel: Add Rocket Lake CPU support
  perf,mm: Handle non-page-table-aligned hugetlbfs
  ...
parents e857b6fc c2208046

arch/arm64/include/asm/pgtable.h

+4 −0
Original line number Diff line number Diff line
@@ -415,6 +415,7 @@ static inline int pmd_trans_huge(pmd_t pmd) 
#define pmd_dirty(pmd)		pte_dirty(pmd_pte(pmd))

#define pmd_young(pmd)		pte_young(pmd_pte(pmd))

#define pmd_valid(pmd)		pte_valid(pmd_pte(pmd))

#define pmd_cont(pmd)		pte_cont(pmd_pte(pmd))

#define pmd_wrprotect(pmd)	pte_pmd(pte_wrprotect(pmd_pte(pmd)))

#define pmd_mkold(pmd)		pte_pmd(pte_mkold(pmd_pte(pmd)))

#define pmd_mkwrite(pmd)	pte_pmd(pte_mkwrite(pmd_pte(pmd)))
@@ -511,6 +512,9 @@ extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, 
				 PMD_TYPE_SECT)

#define pmd_leaf(pmd)		pmd_sect(pmd)



#define pmd_leaf_size(pmd)	(pmd_cont(pmd) ? CONT_PMD_SIZE : PMD_SIZE)

#define pte_leaf_size(pte)	(pte_cont(pte) ? CONT_PTE_SIZE : PAGE_SIZE)



#if defined(CONFIG_ARM64_64K_PAGES) || CONFIG_PGTABLE_LEVELS < 3

static inline bool pud_sect(pud_t pud) { return false; }

static inline bool pud_table(pud_t pud) { return true; }

arch/powerpc/include/asm/nohash/32/pte-8xx.h

+23 −0
Original line number Diff line number Diff line
@@ -135,6 +135,29 @@ static inline pte_t pte_mkhuge(pte_t pte) 
}



#define pte_mkhuge pte_mkhuge



static inline unsigned long pgd_leaf_size(pgd_t pgd)

{

	if (pgd_val(pgd) & _PMD_PAGE_8M)

		return SZ_8M;

	return SZ_4M;

}



#define pgd_leaf_size pgd_leaf_size



static inline unsigned long pte_leaf_size(pte_t pte)

{

	pte_basic_t val = pte_val(pte);



	if (val & _PAGE_HUGE)

		return SZ_512K;

	if (val & _PAGE_SPS)

		return SZ_16K;

	return SZ_4K;

}



#define pte_leaf_size pte_leaf_size



#endif



#endif /* __KERNEL__ */

arch/powerpc/perf/core-book3s.c

+4 −2
Original line number Diff line number Diff line
@@ -2074,6 +2074,9 @@ static struct pmu power_pmu = { 
	.sched_task	= power_pmu_sched_task,

};



#define PERF_SAMPLE_ADDR_TYPE  (PERF_SAMPLE_ADDR |		\

				PERF_SAMPLE_PHYS_ADDR |		\

				PERF_SAMPLE_DATA_PAGE_SIZE)

/*

 * A counter has overflowed; update its count and record

 * things if requested.  Note that interrupts are hard-disabled
@@ -2129,8 +2132,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val, 


		perf_sample_data_init(&data, ~0ULL, event->hw.last_period);



		if (event->attr.sample_type &

		    (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR))

		if (event->attr.sample_type & PERF_SAMPLE_ADDR_TYPE)

			perf_get_data_addr(event, regs, &data.addr);



		if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {

arch/sparc/include/asm/pgtable_64.h

+13 −0
Original line number Diff line number Diff line
@@ -1121,6 +1121,19 @@ extern unsigned long cmdline_memory_size; 


asmlinkage void do_sparc64_fault(struct pt_regs *regs);



#ifdef CONFIG_HUGETLB_PAGE



#define pud_leaf_size pud_leaf_size

extern unsigned long pud_leaf_size(pud_t pud);



#define pmd_leaf_size pmd_leaf_size

extern unsigned long pmd_leaf_size(pmd_t pmd);



#define pte_leaf_size pte_leaf_size

extern unsigned long pte_leaf_size(pte_t pte);



#endif /* CONFIG_HUGETLB_PAGE */



#endif /* !(__ASSEMBLY__) */



#endif /* !(_SPARC64_PGTABLE_H) */

arch/sparc/mm/hugetlbpage.c

+13 −6
Original line number Diff line number Diff line
@@ -247,14 +247,17 @@ static unsigned int sun4u_huge_tte_to_shift(pte_t entry) 
	return shift;

}



static unsigned int huge_tte_to_shift(pte_t entry)

static unsigned long tte_to_shift(pte_t entry)

{

	unsigned long shift;



	if (tlb_type == hypervisor)

		shift = sun4v_huge_tte_to_shift(entry);

	else

		shift = sun4u_huge_tte_to_shift(entry);

		return sun4v_huge_tte_to_shift(entry);



	return sun4u_huge_tte_to_shift(entry);

}



static unsigned int huge_tte_to_shift(pte_t entry)

{

	unsigned long shift = tte_to_shift(entry);



	if (shift == PAGE_SHIFT)

		WARN_ONCE(1, "tto_to_shift: invalid hugepage tte=0x%lx\n",
@@ -272,6 +275,10 @@ static unsigned long huge_tte_to_size(pte_t pte) 
	return size;

}



unsigned long pud_leaf_size(pud_t pud) { return 1UL << tte_to_shift(*(pte_t *)&pud); }

unsigned long pmd_leaf_size(pmd_t pmd) { return 1UL << tte_to_shift(*(pte_t *)&pmd); }

unsigned long pte_leaf_size(pte_t pte) { return 1UL << tte_to_shift(pte); }



pte_t *huge_pte_alloc(struct mm_struct *mm,

			unsigned long addr, unsigned long sz)

{