Commit 8a4ab218 authored by Bradley Hughes's avatar Bradley Hughes Committed by Kumar Gala
Browse files

powerpc/85xx: Change deprecated binding for 85xx-based boards 



The "fsl,85..." style compatible binding was to be deprecated
some time ago.  This patch corrects existing occurrences of
the incorrect binding.  The memory-controller and
l2-cache-controller are the only affected nodes.

Signed-off-by: default avatarBradley Hughes <bhughes@silicontkx.com>
Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent e9502fbe

arch/powerpc/boot/dts/mpc8540ads.dts

+2 −2
Original line number Diff line number Diff line
@@ -71,14 +71,14 @@ 
		};



		memory-controller@2000 {

			compatible = "fsl,8540-memory-controller";

			compatible = "fsl,mpc8540-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <18 2>;

		};



		L2: l2-cache-controller@20000 {

			compatible = "fsl,8540-l2-cache-controller";

			compatible = "fsl,mpc8540-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;	// 32 bytes

			cache-size = <0x40000>;	// L2, 256K

arch/powerpc/boot/dts/mpc8541cds.dts

+2 −2
Original line number Diff line number Diff line
@@ -71,14 +71,14 @@ 
		};



		memory-controller@2000 {

			compatible = "fsl,8541-memory-controller";

			compatible = "fsl,mpc8541-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <18 2>;

		};



		L2: l2-cache-controller@20000 {

			compatible = "fsl,8541-l2-cache-controller";

			compatible = "fsl,mpc8541-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;	// 32 bytes

			cache-size = <0x40000>;	// L2, 256K

arch/powerpc/boot/dts/mpc8544ds.dts

+2 −2
Original line number Diff line number Diff line
@@ -73,14 +73,14 @@ 
		};



		memory-controller@2000 {

			compatible = "fsl,8544-memory-controller";

			compatible = "fsl,mpc8544-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <18 2>;

		};



		L2: l2-cache-controller@20000 {

			compatible = "fsl,8544-l2-cache-controller";

			compatible = "fsl,mpc8544-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;	// 32 bytes

			cache-size = <0x40000>;	// L2, 256K

arch/powerpc/boot/dts/mpc8548cds.dts

+2 −2
Original line number Diff line number Diff line
@@ -74,14 +74,14 @@ 
		};



		memory-controller@2000 {

			compatible = "fsl,8548-memory-controller";

			compatible = "fsl,mpc8548-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <18 2>;

		};



		L2: l2-cache-controller@20000 {

			compatible = "fsl,8548-l2-cache-controller";

			compatible = "fsl,mpc8548-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;	// 32 bytes

			cache-size = <0x80000>;	// L2, 512K

arch/powerpc/boot/dts/mpc8555cds.dts

+2 −2
Original line number Diff line number Diff line
@@ -71,14 +71,14 @@ 
		};



		memory-controller@2000 {

			compatible = "fsl,8555-memory-controller";

			compatible = "fsl,mpc8555-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <18 2>;

		};



		L2: l2-cache-controller@20000 {

			compatible = "fsl,8555-l2-cache-controller";

			compatible = "fsl,mpc8555-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;	// 32 bytes

			cache-size = <0x40000>;	// L2, 256K