Commit 8a3492cd authored by Shubhrajyoti Datta's avatar Shubhrajyoti Datta Committed by Stephen Boyd
Browse files

clk: zynq: pll: Fix kernel-doc warnings 



Fix the following kernel-doc warning

drivers/clk/zynq/pll.c:15: warning: missing initial short description on line:
 * struct zynq_pll
drivers/clk/zynq/pll.c:96: warning: No description found for return value of 'zynq_pll_is_enabled'
drivers/clk/zynq/pll.c:116: warning: No description found for return value of 'zynq_pll_enable'
drivers/clk/zynq/pll.c:187: warning: No description found for return value of 'clk_register_zynq_pll'

Signed-off-by: default avatarShubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Link: https://lore.kernel.org/r/9929a56462bfdd491c43c233abc4341fc14dac1d.1637139796.git.shubhrajyoti.datta@xilinx.com


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 71e76231

drivers/clk/zynq/pll.c

+6 −6
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
#include <linux/io.h>



/**

 * struct zynq_pll

 * struct zynq_pll - pll clock

 * @hw:		Handle between common and hardware-specific interfaces

 * @pll_ctrl:	PLL control register

 * @pll_status:	PLL status register
@@ -46,7 +46,7 @@ struct zynq_pll { 
 * @hw:		Handle between common and hardware-specific interfaces

 * @rate:	Desired clock frequency

 * @prate:	Clock frequency of parent clock

 * Returns frequency closest to @rate the hardware can generate.

 * Return:	frequency closest to @rate the hardware can generate.

 */

static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,

		unsigned long *prate)
@@ -66,7 +66,7 @@ static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate, 
 * zynq_pll_recalc_rate() - Recalculate clock frequency

 * @hw:			Handle between common and hardware-specific interfaces

 * @parent_rate:	Clock frequency of parent clock

 * Returns current clock frequency.

 * Return:		current clock frequency.

 */

static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,

		unsigned long parent_rate)
@@ -87,7 +87,7 @@ static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw, 
/**

 * zynq_pll_is_enabled - Check if a clock is enabled

 * @hw:		Handle between common and hardware-specific interfaces

 * Returns 1 if the clock is enabled, 0 otherwise.

 * Return:	1 if the clock is enabled, 0 otherwise.

 *

 * Not sure this is a good idea, but since disabled means bypassed for

 * this clock implementation we say we are always enabled.
@@ -110,7 +110,7 @@ static int zynq_pll_is_enabled(struct clk_hw *hw) 
/**

 * zynq_pll_enable - Enable clock

 * @hw:		Handle between common and hardware-specific interfaces

 * Returns 0 on success

 * Return: 0 on success

 */

static int zynq_pll_enable(struct clk_hw *hw)

{
@@ -179,7 +179,7 @@ static const struct clk_ops zynq_pll_ops = { 
 * @pll_status:	Pointer to PLL status register

 * @lock_index:	Bit index to this PLL's lock status bit in @pll_status

 * @lock:	Register lock

 * Returns handle to the registered clock.

 * Return:	handle to the registered clock.

 */

struct clk *clk_register_zynq_pll(const char *name, const char *parent,

		void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,