Commit 89fb6500 authored by Richard Weinberger's avatar Richard Weinberger
Browse files

Merge tag 'nand/for-5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next 

Raw NAND controller drivers:
* Intel: Fix an error handling path in 'ebu_dma_start()'
* Tango: Remove the driver
* Marvell: Convert comma to semicolon
* MXC: Convert comma to semicolon
* Qcom: Add support for Qcom SMEM parser

Related MTD changes:
* parsers: Add Qcom SMEM parser
parents 106a3ec3 073abfa7

Documentation/devicetree/bindings/mtd/partitions/qcom,smem-part.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/mtd/partitions/qcom,smem-part.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm SMEM NAND flash partition parser binding



maintainers:

  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>



description: |

  The Qualcomm SoCs supporting the NAND controller interface features a Shared

  Memory (SMEM) based partition table scheme. The maximum partitions supported

  varies between partition table revisions. V3 supports maximum 16 partitions

  and V4 supports 48 partitions.



properties:

  compatible:

    const: qcom,smem-part



required:

  - compatible



additionalProperties: false



examples:

  - |

    flash {

        partitions {

            compatible = "qcom,smem-part";

        };

    };

drivers/mtd/nand/raw/Kconfig

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@@ -102,13 +102,6 @@ config MTD_NAND_S3C2410_CLKSTOP 
	  when the is NAND chip selected or released, but will save

	  approximately 5mA of power when there is nothing happening.



config MTD_NAND_TANGO

	tristate "Tango NAND controller"

	depends on ARCH_TANGO || COMPILE_TEST

	depends on HAS_IOMEM

	help

	  Enables the NAND Flash controller on Tango chips.



config MTD_NAND_SHARPSL

	tristate "Sharp SL Series (C7xx + others) NAND controller"

	depends on ARCH_PXA || COMPILE_TEST

drivers/mtd/nand/raw/Makefile

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@@ -10,7 +10,6 @@ obj-$(CONFIG_MTD_NAND_DENALI_PCI) += denali_pci.o 
obj-$(CONFIG_MTD_NAND_DENALI_DT)	+= denali_dt.o

obj-$(CONFIG_MTD_NAND_AU1550)		+= au1550nd.o

obj-$(CONFIG_MTD_NAND_S3C2410)		+= s3c2410.o

obj-$(CONFIG_MTD_NAND_TANGO)		+= tango_nand.o

obj-$(CONFIG_MTD_NAND_DAVINCI)		+= davinci_nand.o

obj-$(CONFIG_MTD_NAND_DISKONCHIP)	+= diskonchip.o

obj-$(CONFIG_MTD_NAND_FSMC)		+= fsmc_nand.o

drivers/mtd/nand/raw/intel-nand-controller.c

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@@ -318,8 +318,10 @@ static int ebu_dma_start(struct ebu_nand_controller *ebu_host, u32 dir, 
	}



	tx = dmaengine_prep_slave_single(chan, buf_dma, len, dir, flags);

	if (!tx)

		return -ENXIO;

	if (!tx) {

		ret = -ENXIO;

		goto err_unmap;

	}



	tx->callback = callback;

	tx->callback_param = ebu_host;

drivers/mtd/nand/raw/marvell_nand.c

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@@ -2396,7 +2396,7 @@ static int marvell_nfc_setup_interface(struct nand_chip *chip, int chipnr, 
	 * be greater than that to be sure tCCS delay is respected.

	 */

	nfc_tmg.tWHR = TO_CYCLES(max_t(int, sdr->tWHR_min, sdr->tCCS_min),

				 period_ns) - 2,

				 period_ns) - 2;

	nfc_tmg.tRHW = TO_CYCLES(max_t(int, sdr->tRHW_min, sdr->tCCS_min),

				 period_ns);