Commit 89f8a707 authored by Sean Anderson's avatar Sean Anderson Committed by Rob Herring
Browse files

dt-bindings: clk: vc5: Fix example 



The example properties do not match the binding. Fix them, and prohibit
undocumented properties in clock nodes to prevent this from happening in
the future.

Fixes: 45c94018 ("dt-bindings: clk: versaclock5: convert to yaml")
Signed-off-by: default avatarSean Anderson <sean.anderson@seco.com>
Reviewed-by: default avatarLuca Ceresoli <luca@lucaceresoli.net>
Link: https://lore.kernel.org/r/20210607190546.2616259-1-sean.anderson@seco.com


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent cdbbe6ce

Documentation/devicetree/bindings/clock/idt,versaclock5.yaml

+4 −3
Original line number Original line Diff line number Diff line
@@ -86,6 +86,7 @@ patternProperties: 
        description: The Slew rate control for CMOS single-ended.

        description: The Slew rate control for CMOS single-ended.

        $ref: /schemas/types.yaml#/definitions/uint32

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [ 80, 85, 90, 100 ]

        enum: [ 80, 85, 90, 100 ]

    additionalProperties: false





required:

required:

  - compatible

  - compatible
@@ -141,13 +142,13 @@ examples: 
            clock-names = "xin";

            clock-names = "xin";





            OUT1 {

            OUT1 {

                idt,drive-mode = <VC5_CMOSD>;

                idt,mode = <VC5_CMOSD>;

                idt,voltage-microvolts = <1800000>;

                idt,voltage-microvolt = <1800000>;

                idt,slew-percent = <80>;

                idt,slew-percent = <80>;

            };

            };





            OUT4 {

            OUT4 {

                idt,drive-mode = <VC5_LVDS>;

                idt,mode = <VC5_LVDS>;

            };

            };

        };

        };

    };

    };