Commit 89e9fb32 authored by Mark Brown's avatar Mark Brown Committed by Catalin Marinas
Browse files

arm64/sve: Generate ZCR definitions 



Convert the various ZCR instances to automatic generation, no functional
changes expected.

Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Reviewed-by: default avatarMark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20220510161208.631259-13-broonie@kernel.org


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 11e12a91

arch/arm64/include/asm/sysreg.h

+0 −7
Original line number Diff line number Diff line
@@ -213,7 +213,6 @@ 
#define SYS_RGSR_EL1			sys_reg(3, 0, 1, 0, 5)

#define SYS_GCR_EL1			sys_reg(3, 0, 1, 0, 6)



#define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)

#define SYS_TRFCR_EL1			sys_reg(3, 0, 1, 2, 1)



#define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
@@ -558,7 +557,6 @@ 
#define SYS_HFGRTR_EL2			sys_reg(3, 4, 1, 1, 4)

#define SYS_HFGWTR_EL2			sys_reg(3, 4, 1, 1, 5)

#define SYS_HFGITR_EL2			sys_reg(3, 4, 1, 1, 6)

#define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)

#define SYS_TRFCR_EL2			sys_reg(3, 4, 1, 2, 1)

#define SYS_HCRX_EL2			sys_reg(3, 4, 1, 2, 2)

#define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)
@@ -619,7 +617,6 @@ 
/* VHE encodings for architectural EL0/1 system registers */

#define SYS_SCTLR_EL12			sys_reg(3, 5, 1, 0, 0)

#define SYS_CPACR_EL12			sys_reg(3, 5, 1, 0, 2)

#define SYS_ZCR_EL12			sys_reg(3, 5, 1, 2, 0)

#define SYS_TTBR0_EL12			sys_reg(3, 5, 2, 0, 0)

#define SYS_TTBR1_EL12			sys_reg(3, 5, 2, 0, 1)

#define SYS_TCR_EL12			sys_reg(3, 5, 2, 0, 2)
@@ -1101,10 +1098,6 @@ 
#define DCZID_DZP_SHIFT			4

#define DCZID_BS_SHIFT			0



#define ZCR_ELx_LEN_SHIFT	0

#define ZCR_ELx_LEN_WIDTH	4

#define ZCR_ELx_LEN_MASK	0xf



#define CPACR_EL1_FPEN_EL1EN	(BIT(20)) /* enable EL1 access */

#define CPACR_EL1_FPEN_EL0EN	(BIT(21)) /* enable EL0 access, if EL1EN set */

arch/arm64/tools/sysreg

+18 −0
Original line number Diff line number Diff line
@@ -190,6 +190,16 @@ Res0 63:4 
Field	3:0	PRIORITY

EndSysreg



SysregFields	ZCR_ELx

Res0	63:9

Raz	8:4

Field	3:0	LEN

EndSysregFields



Sysreg ZCR_EL1	3	0	1	2	0

Fields ZCR_ELx

EndSysreg



SysregFields	SMCR_ELx

Res0	63:32

Field	31	FA64
@@ -217,6 +227,10 @@ Field 1 ZA 
Field	0	SM

EndSysreg



Sysreg	ZCR_EL2	3	4	1	2	0

Fields	ZCR_ELx

EndSysreg



Sysreg	SMPRIMAP_EL2	3	4	1	2	5

Field	63:60	P15

Field	59:56	P14
@@ -240,6 +254,10 @@ Sysreg SMCR_EL2 3 4 1 2 6 
Fields	SMCR_ELx

EndSysreg



Sysreg	ZCR_EL12	3	5	1	2	0

Fields	ZCR_ELx

EndSysreg



Sysreg	SMCR_EL12	3	5	1	2	6

Fields	SMCR_ELx

EndSysreg