Commit 89a7a870 authored by Andrey Grodzovsky's avatar Andrey Grodzovsky
Browse files

drm/amdgpu: Move in_gpu_reset into reset_domain 



We should have a single instance per entrire reset domain.

Signed-off-by: default avatarAndrey Grodzovsky <andrey.grodzovsky@amd.com>
Suggested-by: default avatarLijo Lazar <lijo.lazar@amd.com>
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Link: https://www.spinics.net/lists/amd-gfx/msg74116.html
parent d0fb18b5

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −5
Original line number Diff line number Diff line
@@ -1056,7 +1056,6 @@ struct amdgpu_device { 
	bool				in_s4;

	bool				in_s0ix;



	atomic_t 			in_gpu_reset;

	enum pp_mp1_state               mp1_state;

	struct amdgpu_doorbell_index doorbell_index;
@@ -1463,8 +1462,6 @@ static inline bool amdgpu_is_tmz(struct amdgpu_device *adev) 
       return adev->gmc.tmz_enabled;

}



static inline int amdgpu_in_reset(struct amdgpu_device *adev)

{

	return atomic_read(&adev->in_gpu_reset);

}

int amdgpu_in_reset(struct amdgpu_device *adev);



#endif

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+7 −3
Original line number Diff line number Diff line
@@ -3554,7 +3554,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, 
	mutex_init(&adev->mn_lock);

	mutex_init(&adev->virt.vf_errors.lock);

	hash_init(adev->mn_hash);

	atomic_set(&adev->in_gpu_reset, 0);

	mutex_init(&adev->psp.mutex);

	mutex_init(&adev->notifier_lock);
@@ -4829,7 +4828,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, 
static void amdgpu_device_lock_adev(struct amdgpu_device *adev,

				struct amdgpu_hive_info *hive)

{

	atomic_set(&adev->in_gpu_reset, 1);

	atomic_set(&adev->reset_domain->in_gpu_reset, 1);



	if (hive) {

		down_write_nest_lock(&adev->reset_domain->sem, &hive->hive_lock);
@@ -4854,7 +4853,7 @@ static void amdgpu_device_unlock_adev(struct amdgpu_device *adev) 
{

	amdgpu_vf_error_trans_all(adev);

	adev->mp1_state = PP_MP1_STATE_NONE;

	atomic_set(&adev->in_gpu_reset, 0);

	atomic_set(&adev->reset_domain->in_gpu_reset, 0);

	up_write(&adev->reset_domain->sem);

}
@@ -5699,6 +5698,11 @@ void amdgpu_device_invalidate_hdp(struct amdgpu_device *adev, 
	amdgpu_asic_invalidate_hdp(adev, ring);

}



int amdgpu_in_reset(struct amdgpu_device *adev)

{

	return atomic_read(&adev->reset_domain->in_gpu_reset);

	}

	

/**

 * amdgpu_device_halt() - bring hardware to some kind of halt state

 *

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c

+1 −0
Original line number Diff line number Diff line
@@ -131,6 +131,7 @@ struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_d 


	}



	atomic_set(&reset_domain->in_gpu_reset, 0);

	init_rwsem(&reset_domain->sem);



	return reset_domain;

drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h

+1 −0
Original line number Diff line number Diff line
@@ -81,6 +81,7 @@ struct amdgpu_reset_domain { 
	struct workqueue_struct *wq;

	enum amdgpu_reset_domain_type type;

	struct rw_semaphore sem;

	atomic_t in_gpu_reset;

};

drivers/gpu/drm/amd/amdgpu/mxgpu_ai.c

+2 −2
Original line number Diff line number Diff line
@@ -259,7 +259,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) 
	 * otherwise the mailbox msg will be ruined/reseted by

	 * the VF FLR.

	 */

	if (atomic_cmpxchg(&adev->in_gpu_reset, 0, 1) != 0)

	if (atomic_cmpxchg(&adev->reset_domain->in_gpu_reset, 0, 1) != 0)

		return;



	down_write(&adev->reset_domain->sem);
@@ -277,7 +277,7 @@ static void xgpu_ai_mailbox_flr_work(struct work_struct *work) 
	} while (timeout > 1);



flr_done:

	atomic_set(&adev->in_gpu_reset, 0);

	atomic_set(&adev->reset_domain->in_gpu_reset, 0);

	up_write(&adev->reset_domain->sem);



	/* Trigger recovery for world switch failure if no TDR */