Unverified Commit 897b0352 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!10411 Intel: Backport 3 core PMU bugfixes to kernel 6.6 

Merge Pull Request from: @yunyingsun 
 
Content:
In mainline kernel before v6.11-rc1, PMU name for Intel next Xeon Granite Rapids(GNR) is the same as 4th and 5th gen Xeon(SPR and EMR). A new bugfix makes GNR using a different name for PMU. 

The fix patch is among a patch set of three which just landed mainline kernel v6.11-rc1:
fa0c1c9d283b perf/x86/intel: Add a distinct name for Granite Rapids
e5f32ad56b22 perf/x86/intel/ds: Fix non 0 retire latency on Raptorlake
556a7c039a52 perf/x86/intel: Hide Topdown metrics events if the feature is not enumerated

This PR is to backport above fixes to kernel 6.6 for better GNR PMU support.

The GNR distinct name patch(fa0c1c9d283b) depends on 6 more commits from mainline kernel v6.7-rc1:
97588df87b56 perf/x86/intel: Add common intel_pmu_init_hybrid()
b0560bfd4b70 perf/x86/intel: Clean up the hybrid CPU type handling code
299a5fc8e783 perf/x86/intel: Apply the common initialization code for ADL
d87d221f854b perf/x86/intel: Factor out the initialization code for ADL e-core
0ba0c03528e9 perf/x86/intel: Factor out the initialization code for SPR
d4b5694c75d4 perf/x86/intel: Use the common uarch name for the shared functions
which introduces some code refactoring in x86 intel PMU driver.

Two more dependent following bugfixes are added for commit 97588df87b56:
(v6.7-rc3) e8df9d9f4209 perf/x86/intel: Correct incorrect 'or' operation for PMU capabilities
(v6.7-rc1) 950ecdc672ae perf/x86/intel: Fix broken fixed event constraints extension

Intel-kernel issue:
https://gitee.com/openeuler/intel-kernel/issues/IAGLFT

Test:
Before backport on GNR, "dmesg | grep -i 'performance events'" shows "Sapphire Rapids events".
After backport on GNR, "dmesg | grep -i 'performance events'" shows "Granite Rapids events".

Known issue:
N/A

Configs:
N/A 
 
Link:https://gitee.com/openeuler/kernel/pulls/10411

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Reviewed-by: default avatarZhang Peng <zhangpeng362@huawei.com>
Signed-off-by: default avatarZhang Peng <zhangpeng362@huawei.com>
parents 669da8f4 6cedcf0d

arch/x86/events/core.c

+3 −3
Original line number Diff line number Diff line
@@ -1890,9 +1890,9 @@ ssize_t events_hybrid_sysfs_show(struct device *dev, 


	str = pmu_attr->event_str;

	for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) {

		if (!(x86_pmu.hybrid_pmu[i].cpu_type & pmu_attr->pmu_type))

		if (!(x86_pmu.hybrid_pmu[i].pmu_type & pmu_attr->pmu_type))

			continue;

		if (x86_pmu.hybrid_pmu[i].cpu_type & pmu->cpu_type) {

		if (x86_pmu.hybrid_pmu[i].pmu_type & pmu->pmu_type) {

			next_str = strchr(str, ';');

			if (next_str)

				return snprintf(page, next_str - str + 1, "%s", str);
@@ -2172,7 +2172,7 @@ static int __init init_hw_perf_events(void) 
			hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_EXTENDED_HW_TYPE;



			err = perf_pmu_register(&hybrid_pmu->pmu, hybrid_pmu->name,

						(hybrid_pmu->cpu_type == hybrid_big) ? PERF_TYPE_RAW : -1);

						(hybrid_pmu->pmu_type == hybrid_big) ? PERF_TYPE_RAW : -1);

			if (err)

				break;

		}

arch/x86/events/intel/core.c

+276 −230

File changed.

Preview size limit exceeded, changes collapsed.

arch/x86/events/intel/ds.c

+2 −2
Original line number Diff line number Diff line
@@ -261,7 +261,7 @@ static u64 __adl_latency_data_small(struct perf_event *event, u64 status, 
{

	u64 val;



	WARN_ON_ONCE(hybrid_pmu(event->pmu)->cpu_type == hybrid_big);

	WARN_ON_ONCE(hybrid_pmu(event->pmu)->pmu_type == hybrid_big);



	dse &= PERF_PEBS_DATA_SOURCE_MASK;

	val = hybrid_var(event->pmu, pebs_data_source)[dse];
@@ -1058,7 +1058,7 @@ struct event_constraint intel_icl_pebs_event_constraints[] = { 
	EVENT_CONSTRAINT_END

};



struct event_constraint intel_spr_pebs_event_constraints[] = {

struct event_constraint intel_glc_pebs_event_constraints[] = {

	INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL),	/* INST_RETIRED.PREC_DIST */

	INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),

arch/x86/events/perf_event.h

+22 −15
Original line number Diff line number Diff line
@@ -658,10 +658,29 @@ enum { 
#define PERF_PEBS_DATA_SOURCE_MAX	0x10

#define PERF_PEBS_DATA_SOURCE_MASK	(PERF_PEBS_DATA_SOURCE_MAX - 1)



enum hybrid_cpu_type {

	HYBRID_INTEL_NONE,

	HYBRID_INTEL_ATOM	= 0x20,

	HYBRID_INTEL_CORE	= 0x40,

};



enum hybrid_pmu_type {

	not_hybrid,

	hybrid_small		= BIT(0),

	hybrid_big		= BIT(1),



	hybrid_big_small	= hybrid_big | hybrid_small, /* only used for matching */

};



#define X86_HYBRID_PMU_ATOM_IDX		0

#define X86_HYBRID_PMU_CORE_IDX		1



#define X86_HYBRID_NUM_PMUS		2



struct x86_hybrid_pmu {

	struct pmu			pmu;

	const char			*name;

	u8				cpu_type;

	enum hybrid_pmu_type		pmu_type;

	cpumask_t			supported_cpus;

	union perf_capabilities		intel_cap;

	u64				intel_ctrl;
@@ -727,18 +746,6 @@ extern struct static_key_false perf_is_hybrid; 
	__Fp;						\

})



enum hybrid_pmu_type {

	hybrid_big		= 0x40,

	hybrid_small		= 0x20,



	hybrid_big_small	= hybrid_big | hybrid_small,

};



#define X86_HYBRID_PMU_ATOM_IDX		0

#define X86_HYBRID_PMU_CORE_IDX		1



#define X86_HYBRID_NUM_PMUS		2



/*

 * struct x86_pmu - generic x86 pmu

 */
@@ -947,7 +954,7 @@ struct x86_pmu { 
	 */

	int				num_hybrid_pmus;

	struct x86_hybrid_pmu		*hybrid_pmu;

	u8 (*get_hybrid_cpu_type)	(void);

	enum hybrid_cpu_type (*get_hybrid_cpu_type)	(void);

};



struct x86_perf_task_context_opt {
@@ -1529,7 +1536,7 @@ extern struct event_constraint intel_skl_pebs_event_constraints[]; 


extern struct event_constraint intel_icl_pebs_event_constraints[];



extern struct event_constraint intel_spr_pebs_event_constraints[];

extern struct event_constraint intel_glc_pebs_event_constraints[];



struct event_constraint *intel_pebs_constraints(struct perf_event *event);