Commit 89688e21 authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Rob Clark
Browse files

drm/msm/dpu: Add more of the INTF interrupt regions 



In addition to the other 7xxx INTF interrupt regions, SM8350 has
additional INTF regions at 0x0ae37000, 0x0ae38000 and 0x0ae39000, define
these. The 7xxx naming scheme of the bits are kept for consistency.

Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: default avatarRobert Foss <robert.foss@linaro.org>
Reviewed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Link: https://lore.kernel.org/r/20211123154050.40984-1-bjorn.andersson@linaro.org


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent fabae667

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c

+18 −0
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ 
#define MDP_AD4_INTR_STATUS_OFF		0x420

#define MDP_INTF_0_OFF_REV_7xxx             0x34000

#define MDP_INTF_1_OFF_REV_7xxx             0x35000

#define MDP_INTF_2_OFF_REV_7xxx             0x36000

#define MDP_INTF_3_OFF_REV_7xxx             0x37000

#define MDP_INTF_4_OFF_REV_7xxx             0x38000

#define MDP_INTF_5_OFF_REV_7xxx             0x39000



/**
@@ -110,6 +113,21 @@ static const struct dpu_intr_reg dpu_intr_set[] = { 
		MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_1_OFF_REV_7xxx+INTF_INTR_STATUS

	},

	{

		MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_2_OFF_REV_7xxx+INTF_INTR_STATUS

	},

	{

		MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_3_OFF_REV_7xxx+INTF_INTR_STATUS

	},

	{

		MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_EN,

		MDP_INTF_4_OFF_REV_7xxx+INTF_INTR_STATUS

	},

	{

		MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_CLEAR,

		MDP_INTF_5_OFF_REV_7xxx+INTF_INTR_EN,

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h

+3 −0
Original line number Diff line number Diff line
@@ -26,6 +26,9 @@ enum dpu_hw_intr_reg { 
	MDP_AD4_1_INTR,

	MDP_INTF0_7xxx_INTR,

	MDP_INTF1_7xxx_INTR,

	MDP_INTF2_7xxx_INTR,

	MDP_INTF3_7xxx_INTR,

	MDP_INTF4_7xxx_INTR,

	MDP_INTF5_7xxx_INTR,

	MDP_INTR_MAX,

};