Commit 8947c390 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'mlxsw-add-spectrum-4-support'

Ido Schimmel says:

====================
mlxsw: Add Spectrum-4 support

This patchset adds Spectrum-4 support in mlxsw. It builds on top of a
previous patchset merged in commit 10184da9 ("Merge branch
'mlxsw-Spectrum-4-prep'") and makes two additional changes before adding
Spectrum-4 support.

Patchset overview:

Patches #1-#2 add a few Spectrum-4 specific variants of existing ACL
keys. The new variants are needed because the size of certain key
elements (e.g., local port) was increased in Spectrum-4.

Patches #3-#6 are preparations.

Patch #7 implements the Spectrum-4 variant of the Bloom filter hash
function. The Bloom filter is used to optimize ACL lookups by
potentially skipping certain lookups if they are guaranteed not to
match. See additional info in merge commit ae6750e0 ("Merge branch
'mlxsw-spectrum_acl-Add-Bloom-filter-support'").

Patch #8 finally adds Spectrum-4 support.
====================

Link: https://lore.kernel.org/r/20220106160652.821176-1-idosch@nvidia.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 42379b95 47354021
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+1 −1
Original line number Diff line number Diff line
@@ -66,7 +66,7 @@ config MLXSW_SPECTRUM
	default m
	help
	  This driver supports Mellanox Technologies
	  Spectrum/Spectrum-2/Spectrum-3 Ethernet Switch ASICs.
	  Spectrum/Spectrum-2/Spectrum-3/Spectrum-4 Ethernet Switch ASICs.

	  To compile this driver as a module, choose M here: the
	  module will be called mlxsw_spectrum.
+2 −2
Original line number Diff line number Diff line
@@ -32,8 +32,8 @@ static const struct mlxsw_afk_element_info mlxsw_afk_element_infos[] = {
	MLXSW_AFK_ELEMENT_INFO_U32(IP_TTL_, 0x18, 0, 8),
	MLXSW_AFK_ELEMENT_INFO_U32(IP_ECN, 0x18, 9, 2),
	MLXSW_AFK_ELEMENT_INFO_U32(IP_DSCP, 0x18, 11, 6),
	MLXSW_AFK_ELEMENT_INFO_U32(VIRT_ROUTER_8_10, 0x18, 17, 3),
	MLXSW_AFK_ELEMENT_INFO_U32(VIRT_ROUTER_0_7, 0x18, 20, 8),
	MLXSW_AFK_ELEMENT_INFO_U32(VIRT_ROUTER_MSB, 0x18, 17, 3),
	MLXSW_AFK_ELEMENT_INFO_U32(VIRT_ROUTER_LSB, 0x18, 20, 8),
	MLXSW_AFK_ELEMENT_INFO_BUF(SRC_IP_96_127, 0x20, 4),
	MLXSW_AFK_ELEMENT_INFO_BUF(SRC_IP_64_95, 0x24, 4),
	MLXSW_AFK_ELEMENT_INFO_BUF(SRC_IP_32_63, 0x28, 4),
+2 −2
Original line number Diff line number Diff line
@@ -33,8 +33,8 @@ enum mlxsw_afk_element {
	MLXSW_AFK_ELEMENT_IP_TTL_,
	MLXSW_AFK_ELEMENT_IP_ECN,
	MLXSW_AFK_ELEMENT_IP_DSCP,
	MLXSW_AFK_ELEMENT_VIRT_ROUTER_8_10,
	MLXSW_AFK_ELEMENT_VIRT_ROUTER_0_7,
	MLXSW_AFK_ELEMENT_VIRT_ROUTER_MSB,
	MLXSW_AFK_ELEMENT_VIRT_ROUTER_LSB,
	MLXSW_AFK_ELEMENT_MAX,
};

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@
#define PCI_DEVICE_ID_MELLANOX_SPECTRUM		0xcb84
#define PCI_DEVICE_ID_MELLANOX_SPECTRUM2	0xcf6c
#define PCI_DEVICE_ID_MELLANOX_SPECTRUM3	0xcf70
#define PCI_DEVICE_ID_MELLANOX_SPECTRUM4	0xcf80

#if IS_ENABLED(CONFIG_MLXSW_PCI)

+1 −0
Original line number Diff line number Diff line
@@ -3914,6 +3914,7 @@ MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1	5
#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2	11
#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3	11
#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP4	11

static inline void mlxsw_reg_qeec_pack(char *payload, u16 local_port,
				       enum mlxsw_reg_qeec_hr hr, u8 index,
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