Merge tag 'perf-tools-fixes-for-v5.19-2022-06-26' of... (893d1eaa) · Commits · EulixOS / Software / Kernel

tools/arch/x86/include/asm/cpufeatures.h

+5 −2

Original line number	Diff line number	Diff line
		@@ -201,7 +201,7 @@
		#define X86_FEATURE_INVPCID_SINGLE ( 732+ 7) / Effectively INVPCID && CR4.PCIDE=1 */
		#define X86_FEATURE_HW_PSTATE ( 732+ 8) / AMD HW-PState */
		#define X86_FEATURE_PROC_FEEDBACK ( 732+ 9) / AMD ProcFeedbackInterface */
		/* FREE! ( 732+10) /
		#define X86_FEATURE_XCOMPACTED ( 732+10) / "" Use compacted XSTATE (XSAVES or XSAVEC) */
		#define X86_FEATURE_PTI ( 732+11) / Kernel Page Table Isolation enabled */
		#define X86_FEATURE_RETPOLINE ( 732+12) / "" Generic Retpoline mitigation for Spectre variant 2 */
		#define X86_FEATURE_RETPOLINE_LFENCE ( 732+13) / "" Use LFENCE for Spectre variant 2 */
		@@ -211,7 +211,7 @@
		#define X86_FEATURE_SSBD ( 732+17) / Speculative Store Bypass Disable */
		#define X86_FEATURE_MBA ( 732+18) / Memory Bandwidth Allocation */
		#define X86_FEATURE_RSB_CTXSW ( 732+19) / "" Fill RSB on context switches */
		/* FREE! ( 732+20) /
		#define X86_FEATURE_PERFMON_V2 ( 732+20) / AMD Performance Monitoring Version 2 */
		#define X86_FEATURE_USE_IBPB ( 732+21) / "" Indirect Branch Prediction Barrier enabled */
		#define X86_FEATURE_USE_IBRS_FW ( 732+22) / "" Use IBRS during runtime firmware calls */
		#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 732+23) / "" Disable Speculative Store Bypass. */
		@@ -238,6 +238,7 @@
		#define X86_FEATURE_VMW_VMMCALL ( 832+19) / "" VMware prefers VMMCALL hypercall instruction */
		#define X86_FEATURE_PVUNLOCK ( 832+20) / "" PV unlock function */
		#define X86_FEATURE_VCPUPREEMPT ( 832+21) / "" PV vcpu_is_preempted function */
		#define X86_FEATURE_TDX_GUEST ( 832+22) / Intel Trust Domain Extensions Guest */

		/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
		#define X86_FEATURE_FSGSBASE ( 932+ 0) / RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
		@@ -315,6 +316,7 @@
		#define X86_FEATURE_VIRT_SSBD (1332+25) / Virtualized Speculative Store Bypass Disable */
		#define X86_FEATURE_AMD_SSB_NO (1332+26) / "" Speculative Store Bypass is fixed in hardware. */
		#define X86_FEATURE_CPPC (1332+27) / Collaborative Processor Performance Control */
		#define X86_FEATURE_BRS (1332+31) / Branch Sampling available */

		/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
		#define X86_FEATURE_DTHERM (1432+ 0) / Digital Thermal Sensor */
		@@ -405,6 +407,7 @@
		#define X86_FEATURE_SEV (1932+ 1) / AMD Secure Encrypted Virtualization */
		#define X86_FEATURE_VM_PAGE_FLUSH (1932+ 2) / "" VM Page Flush MSR is supported */
		#define X86_FEATURE_SEV_ES (1932+ 3) / AMD Secure Encrypted Virtualization - Encrypted State */
		#define X86_FEATURE_V_TSC_AUX (1932+ 9) / "" Virtual TSC_AUX */
		#define X86_FEATURE_SME_COHERENT (1932+10) / "" AMD hardware-enforced cache coherency */

		/*

tools/arch/x86/include/asm/disabled-features.h

+7 −1

Original line number	Diff line number	Diff line
		@@ -62,6 +62,12 @@
		# define DISABLE_SGX (1 << (X86_FEATURE_SGX & 31))
		#endif

		#ifdef CONFIG_INTEL_TDX_GUEST
		# define DISABLE_TDX_GUEST 0
		#else
		# define DISABLE_TDX_GUEST (1 << (X86_FEATURE_TDX_GUEST & 31))
		#endif

		/*
		* Make sure to add features to the correct mask
		*/
		@@ -73,7 +79,7 @@
		#define DISABLED_MASK5 0
		#define DISABLED_MASK6 0
		#define DISABLED_MASK7 (DISABLE_PTI)
		#define DISABLED_MASK8 0
		#define DISABLED_MASK8 (DISABLE_TDX_GUEST)
		#define DISABLED_MASK9 (DISABLE_SGX)
		#define DISABLED_MASK10 0
		#define DISABLED_MASK11 0

tools/arch/x86/include/uapi/asm/svm.h

+13 −0

Original line number	Diff line number	Diff line
		@@ -108,6 +108,14 @@
		#define SVM_VMGEXIT_AP_JUMP_TABLE 0x80000005
		#define SVM_VMGEXIT_SET_AP_JUMP_TABLE 0
		#define SVM_VMGEXIT_GET_AP_JUMP_TABLE 1
		#define SVM_VMGEXIT_PSC 0x80000010
		#define SVM_VMGEXIT_GUEST_REQUEST 0x80000011
		#define SVM_VMGEXIT_EXT_GUEST_REQUEST 0x80000012
		#define SVM_VMGEXIT_AP_CREATION 0x80000013
		#define SVM_VMGEXIT_AP_CREATE_ON_INIT 0
		#define SVM_VMGEXIT_AP_CREATE 1
		#define SVM_VMGEXIT_AP_DESTROY 2
		#define SVM_VMGEXIT_HV_FEATURES 0x8000fffd
		#define SVM_VMGEXIT_UNSUPPORTED_EVENT 0x8000ffff

		/* Exit code reserved for hypervisor/software use */
		@@ -218,6 +226,11 @@
		{ SVM_VMGEXIT_NMI_COMPLETE, "vmgexit_nmi_complete" }, \
		{ SVM_VMGEXIT_AP_HLT_LOOP, "vmgexit_ap_hlt_loop" }, \
		{ SVM_VMGEXIT_AP_JUMP_TABLE, "vmgexit_ap_jump_table" }, \
		{ SVM_VMGEXIT_PSC, "vmgexit_page_state_change" }, \
		{ SVM_VMGEXIT_GUEST_REQUEST, "vmgexit_guest_request" }, \
		{ SVM_VMGEXIT_EXT_GUEST_REQUEST, "vmgexit_ext_guest_request" }, \
		{ SVM_VMGEXIT_AP_CREATION, "vmgexit_ap_creation" }, \
		{ SVM_VMGEXIT_HV_FEATURES, "vmgexit_hypervisor_feature" }, \
		{ SVM_EXIT_ERR, "invalid_guest_state" }

tools/include/uapi/drm/i915_drm.h

+272 −81

Original line number	Diff line number	Diff line
		@@ -154,25 +154,77 @@ enum i915_mocs_table_index {
		I915_MOCS_CACHED,
		};

		/*
		/**
		* enum drm_i915_gem_engine_class - uapi engine type enumeration
		*
		* Different engines serve different roles, and there may be more than one
		* engine serving each role. enum drm_i915_gem_engine_class provides a
		* classification of the role of the engine, which may be used when requesting
		* operations to be performed on a certain subset of engines, or for providing
		* information about that group.
		* engine serving each role. This enum provides a classification of the role
		* of the engine, which may be used when requesting operations to be performed
		* on a certain subset of engines, or for providing information about that
		* group.
		*/
		enum drm_i915_gem_engine_class {
		/**
		* @I915_ENGINE_CLASS_RENDER:
		*
		* Render engines support instructions used for 3D, Compute (GPGPU),
		* and programmable media workloads. These instructions fetch data and
		* dispatch individual work items to threads that operate in parallel.
		* The threads run small programs (called "kernels" or "shaders") on
		* the GPU's execution units (EUs).
		*/
		I915_ENGINE_CLASS_RENDER = 0,

		/**
		* @I915_ENGINE_CLASS_COPY:
		*
		* Copy engines (also referred to as "blitters") support instructions
		* that move blocks of data from one location in memory to another,
		* or that fill a specified location of memory with fixed data.
		* Copy engines can perform pre-defined logical or bitwise operations
		* on the source, destination, or pattern data.
		*/
		I915_ENGINE_CLASS_COPY = 1,

		/**
		* @I915_ENGINE_CLASS_VIDEO:
		*
		* Video engines (also referred to as "bit stream decode" (BSD) or
		* "vdbox") support instructions that perform fixed-function media
		* decode and encode.
		*/
		I915_ENGINE_CLASS_VIDEO = 2,

		/**
		* @I915_ENGINE_CLASS_VIDEO_ENHANCE:
		*
		* Video enhancement engines (also referred to as "vebox") support
		* instructions related to image enhancement.
		*/
		I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,

		/* should be kept compact */
		/**
		* @I915_ENGINE_CLASS_COMPUTE:
		*
		* Compute engines support a subset of the instructions available
		* on render engines: compute engines support Compute (GPGPU) and
		* programmable media workloads, but do not support the 3D pipeline.
		*/
		I915_ENGINE_CLASS_COMPUTE = 4,

		/* Values in this enum should be kept compact. */

		/**
		* @I915_ENGINE_CLASS_INVALID:
		*
		* Placeholder value to represent an invalid engine class assignment.
		*/
		I915_ENGINE_CLASS_INVALID = -1
		};

		/*
		/**
		* struct i915_engine_class_instance - Engine class/instance identifier
		*
		* There may be more than one engine fulfilling any role within the system.
		* Each engine of a class is given a unique instance number and therefore
		* any engine can be specified by its class:instance tuplet. APIs that allow
		@@ -180,10 +232,21 @@ enum drm_i915_gem_engine_class {
		* for this identification.
		*/
		struct i915_engine_class_instance {
		__u16 engine_class; /* see enum drm_i915_gem_engine_class */
		__u16 engine_instance;
		/**
		* @engine_class:
		*
		* Engine class from enum drm_i915_gem_engine_class
		*/
		__u16 engine_class;
		#define I915_ENGINE_CLASS_INVALID_NONE -1
		#define I915_ENGINE_CLASS_INVALID_VIRTUAL -2

		/**
		* @engine_instance:
		*
		* Engine instance.
		*/
		__u16 engine_instance;
		};

		/**
		@@ -2657,24 +2720,65 @@ enum drm_i915_perf_record_type {
		DRM_I915_PERF_RECORD_MAX /* non-ABI */
		};

		/*
		/**
		* struct drm_i915_perf_oa_config
		*
		* Structure to upload perf dynamic configuration into the kernel.
		*/
		struct drm_i915_perf_oa_config {
		/** String formatted like "%08x-%04x-%04x-%04x-%012x" */
		/**
		* @uuid:
		*
		* String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
		*/
		char uuid[36];

		/**
		* @n_mux_regs:
		*
		* Number of mux regs in &mux_regs_ptr.
		*/
		__u32 n_mux_regs;

		/**
		* @n_boolean_regs:
		*
		* Number of boolean regs in &boolean_regs_ptr.
		*/
		__u32 n_boolean_regs;

		/**
		* @n_flex_regs:
		*
		* Number of flex regs in &flex_regs_ptr.
		*/
		__u32 n_flex_regs;

		/*
		* These fields are pointers to tuples of u32 values (register address,
		* value). For example the expected length of the buffer pointed by
		* mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs).
		/**
		* @mux_regs_ptr:
		*
		* Pointer to tuples of u32 values (register address, value) for mux
		* registers. Expected length of buffer is (2 * sizeof(u32) *
		* &n_mux_regs).
		*/
		__u64 mux_regs_ptr;

		/**
		* @boolean_regs_ptr:
		*
		* Pointer to tuples of u32 values (register address, value) for mux
		* registers. Expected length of buffer is (2 * sizeof(u32) *
		* &n_boolean_regs).
		*/
		__u64 boolean_regs_ptr;

		/**
		* @flex_regs_ptr:
		*
		* Pointer to tuples of u32 values (register address, value) for mux
		* registers. Expected length of buffer is (2 * sizeof(u32) *
		* &n_flex_regs).
		*/
		__u64 flex_regs_ptr;
		};

		@@ -2685,12 +2789,24 @@ struct drm_i915_perf_oa_config {
		* @data_ptr is also depends on the specific @query_id.
		*/
		struct drm_i915_query_item {
		/** @query_id: The id for this query */
		/**
		* @query_id:
		*
		* The id for this query. Currently accepted query IDs are:
		* - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info)
		* - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
		* - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config)
		* - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions)
		* - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
		* - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info)
		*/
		__u64 query_id;
		#define DRM_I915_QUERY_TOPOLOGY_INFO 1
		#define DRM_I915_QUERY_ENGINE_INFO 2
		#define DRM_I915_QUERY_PERF_CONFIG 3
		#define DRM_I915_QUERY_MEMORY_REGIONS 4
		#define DRM_I915_QUERY_HWCONFIG_BLOB 5
		#define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
		/* Must be kept compact -- no holes and well documented */

		/**
		@@ -2706,14 +2822,17 @@ struct drm_i915_query_item {
		/**
		* @flags:
		*
		* When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
		* When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
		*
		* When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
		* When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
		* following:
		*
		* - DRM_I915_QUERY_PERF_CONFIG_LIST
		* - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
		* - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
		* - %DRM_I915_QUERY_PERF_CONFIG_LIST
		* - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
		* - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
		*
		* When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain
		* a struct i915_engine_class_instance that references a render engine.
		*/
		__u32 flags;
		#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
		@@ -2771,66 +2890,112 @@ struct drm_i915_query {
		__u64 items_ptr;
		};

		/*
		* Data written by the kernel with query DRM_I915_QUERY_TOPOLOGY_INFO :
		*
		* data: contains the 3 pieces of information :
		*
		* - the slice mask with one bit per slice telling whether a slice is
		* available. The availability of slice X can be queried with the following
		* formula :
		*
		* (data[X / 8] >> (X % 8)) & 1
		*
		* - the subslice mask for each slice with one bit per subslice telling
		* whether a subslice is available. Gen12 has dual-subslices, which are
		* similar to two gen11 subslices. For gen12, this array represents dual-
		* subslices. The availability of subslice Y in slice X can be queried
		* with the following formula :
		*
		* (data[subslice_offset +
		* X * subslice_stride +
		* Y / 8] >> (Y % 8)) & 1
		*
		* - the EU mask for each subslice in each slice with one bit per EU telling
		* whether an EU is available. The availability of EU Z in subslice Y in
		* slice X can be queried with the following formula :
		/**
		* struct drm_i915_query_topology_info
		*
		* (data[eu_offset +
		* (X * max_subslices + Y) * eu_stride +
		* Z / 8] >> (Z % 8)) & 1
		* Describes slice/subslice/EU information queried by
		* %DRM_I915_QUERY_TOPOLOGY_INFO
		*/
		struct drm_i915_query_topology_info {
		/*
		/**
		* @flags:
		*
		* Unused for now. Must be cleared to zero.
		*/
		__u16 flags;

		/**
		* @max_slices:
		*
		* The number of bits used to express the slice mask.
		*/
		__u16 max_slices;

		/**
		* @max_subslices:
		*
		* The number of bits used to express the subslice mask.
		*/
		__u16 max_subslices;

		/**
		* @max_eus_per_subslice:
		*
		* The number of bits in the EU mask that correspond to a single
		* subslice's EUs.
		*/
		__u16 max_eus_per_subslice;

		/*
		/**
		* @subslice_offset:
		*
		* Offset in data[] at which the subslice masks are stored.
		*/
		__u16 subslice_offset;

		/*
		/**
		* @subslice_stride:
		*
		* Stride at which each of the subslice masks for each slice are
		* stored.
		*/
		__u16 subslice_stride;

		/*
		/**
		* @eu_offset:
		*
		* Offset in data[] at which the EU masks are stored.
		*/
		__u16 eu_offset;

		/*
		/**
		* @eu_stride:
		*
		* Stride at which each of the EU masks for each subslice are stored.
		*/
		__u16 eu_stride;

		/**
		* @data:
		*
		* Contains 3 pieces of information :
		*
		* - The slice mask with one bit per slice telling whether a slice is
		* available. The availability of slice X can be queried with the
		* following formula :
		*
		* .. code:: c
		*
		* (data[X / 8] >> (X % 8)) & 1
		*
		* Starting with Xe_HP platforms, Intel hardware no longer has
		* traditional slices so i915 will always report a single slice
		* (hardcoded slicemask = 0x1) which contains all of the platform's
		* subslices. I.e., the mask here does not reflect any of the newer
		* hardware concepts such as "gslices" or "cslices" since userspace
		* is capable of inferring those from the subslice mask.
		*
		* - The subslice mask for each slice with one bit per subslice telling
		* whether a subslice is available. Starting with Gen12 we use the
		* term "subslice" to refer to what the hardware documentation
		* describes as a "dual-subslices." The availability of subslice Y
		* in slice X can be queried with the following formula :
		*
		* .. code:: c
		*
		* (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1
		*
		* - The EU mask for each subslice in each slice, with one bit per EU
		* telling whether an EU is available. The availability of EU Z in
		* subslice Y in slice X can be queried with the following formula :
		*
		* .. code:: c
		*
		* (data[eu_offset +
		* (X * max_subslices + Y) * eu_stride +
		* Z / 8
		* ] >> (Z % 8)) & 1
		*/
		__u8 data[];
		};

		@@ -2951,52 +3116,68 @@ struct drm_i915_query_engine_info {
		struct drm_i915_engine_info engines[];
		};

		/*
		* Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
		/**
		* struct drm_i915_query_perf_config
		*
		* Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and
		* %DRM_I915_QUERY_GEOMETRY_SUBSLICES.
		*/
		struct drm_i915_query_perf_config {
		union {
		/*
		* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
		* this fields to the number of configurations available.
		/**
		* @n_configs:
		*
		* When &drm_i915_query_item.flags ==
		* %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
		* the number of configurations available.
		*/
		__u64 n_configs;

		/*
		* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
		* i915 will use the value in this field as configuration
		* identifier to decide what data to write into config_ptr.
		/**
		* @config:
		*
		* When &drm_i915_query_item.flags ==
		* %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
		* value in this field as configuration identifier to decide
		* what data to write into config_ptr.
		*/
		__u64 config;

		/*
		* When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
		* i915 will use the value in this field as configuration
		* identifier to decide what data to write into config_ptr.
		/**
		* @uuid:
		*
		* When &drm_i915_query_item.flags ==
		* %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
		* value in this field as configuration identifier to decide
		* what data to write into config_ptr.
		*
		* String formatted like "%08x-%04x-%04x-%04x-%012x"
		*/
		char uuid[36];
		};

		/*
		/**
		* @flags:
		*
		* Unused for now. Must be cleared to zero.
		*/
		__u32 flags;

		/*
		* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
		* write an array of __u64 of configuration identifiers.
		/**
		* @data:
		*
		* When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
		* write a struct drm_i915_perf_oa_config. If the following fields of
		* drm_i915_perf_oa_config are set not set to 0, i915 will write into
		* the associated pointers the values of submitted when the
		* When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST,
		* i915 will write an array of __u64 of configuration identifiers.
		*
		* When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA,
		* i915 will write a struct drm_i915_perf_oa_config. If the following
		* fields of struct drm_i915_perf_oa_config are not set to 0, i915 will
		* write into the associated pointers the values of submitted when the
		* configuration was created :
		*
		* - n_mux_regs
		* - n_boolean_regs
		* - n_flex_regs
		* - &drm_i915_perf_oa_config.n_mux_regs
		* - &drm_i915_perf_oa_config.n_boolean_regs
		* - &drm_i915_perf_oa_config.n_flex_regs
		*/
		__u8 data[];
		};
		@@ -3134,6 +3315,16 @@ struct drm_i915_query_memory_regions {
		struct drm_i915_memory_region_info regions[];
		};

		/**
		* DOC: GuC HWCONFIG blob uAPI
		*
		* The GuC produces a blob with information about the current device.
		* i915 reads this blob from GuC and makes it available via this uAPI.
		*
		* The format and meaning of the blob content are documented in the
		* Programmer's Reference Manual.
		*/

		/**
		* struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
		* extension support using struct i915_user_extension.

tools/include/uapi/linux/vhost.h

+20 −6

Original line number	Diff line number	Diff line
		@@ -89,11 +89,6 @@

		/* Set or get vhost backend capability */

		/* Use message type V2 */
		#define VHOST_BACKEND_F_IOTLB_MSG_V2 0x1
		/* IOTLB can accept batching hints */
		#define VHOST_BACKEND_F_IOTLB_BATCH 0x2

		#define VHOST_SET_BACKEND_FEATURES _IOW(VHOST_VIRTIO, 0x25, __u64)
		#define VHOST_GET_BACKEND_FEATURES _IOR(VHOST_VIRTIO, 0x26, __u64)

		@@ -150,11 +145,30 @@
		/* Get the valid iova range */
		#define VHOST_VDPA_GET_IOVA_RANGE _IOR(VHOST_VIRTIO, 0x78, \
		struct vhost_vdpa_iova_range)

		/* Get the config size */
		#define VHOST_VDPA_GET_CONFIG_SIZE _IOR(VHOST_VIRTIO, 0x79, __u32)

		/* Get the count of all virtqueues */
		#define VHOST_VDPA_GET_VQS_COUNT _IOR(VHOST_VIRTIO, 0x80, __u32)

		/* Get the number of virtqueue groups. */
		#define VHOST_VDPA_GET_GROUP_NUM _IOR(VHOST_VIRTIO, 0x81, __u32)

		/* Get the number of address spaces. */
		#define VHOST_VDPA_GET_AS_NUM _IOR(VHOST_VIRTIO, 0x7A, unsigned int)

		/* Get the group for a virtqueue: read index, write group in num,
		* The virtqueue index is stored in the index field of
		* vhost_vring_state. The group for this specific virtqueue is
		* returned via num field of vhost_vring_state.
		*/
		#define VHOST_VDPA_GET_VRING_GROUP _IOWR(VHOST_VIRTIO, 0x7B, \
		struct vhost_vring_state)
		/* Set the ASID for a virtqueue group. The group index is stored in
		* the index field of vhost_vring_state, the ASID associated with this
		* group is stored at num field of vhost_vring_state.
		*/
		#define VHOST_VDPA_SET_GROUP_ASID _IOW(VHOST_VIRTIO, 0x7C, \
		struct vhost_vring_state)

		#endif

Original line number	Diff line number	Diff line
		@@ -201,7 +201,7 @@
		#define X86_FEATURE_INVPCID_SINGLE ( 732+ 7) / Effectively INVPCID && CR4.PCIDE=1 */
		#define X86_FEATURE_HW_PSTATE ( 732+ 8) / AMD HW-PState */
		#define X86_FEATURE_PROC_FEEDBACK ( 732+ 9) / AMD ProcFeedbackInterface */
		/* FREE! ( 732+10) /
		#define X86_FEATURE_XCOMPACTED ( 732+10) / "" Use compacted XSTATE (XSAVES or XSAVEC) */
		#define X86_FEATURE_PTI ( 732+11) / Kernel Page Table Isolation enabled */
		#define X86_FEATURE_RETPOLINE ( 732+12) / "" Generic Retpoline mitigation for Spectre variant 2 */
		#define X86_FEATURE_RETPOLINE_LFENCE ( 732+13) / "" Use LFENCE for Spectre variant 2 */
		@@ -211,7 +211,7 @@
		#define X86_FEATURE_SSBD ( 732+17) / Speculative Store Bypass Disable */
		#define X86_FEATURE_MBA ( 732+18) / Memory Bandwidth Allocation */
		#define X86_FEATURE_RSB_CTXSW ( 732+19) / "" Fill RSB on context switches */
		/* FREE! ( 732+20) /
		#define X86_FEATURE_PERFMON_V2 ( 732+20) / AMD Performance Monitoring Version 2 */
		#define X86_FEATURE_USE_IBPB ( 732+21) / "" Indirect Branch Prediction Barrier enabled */
		#define X86_FEATURE_USE_IBRS_FW ( 732+22) / "" Use IBRS during runtime firmware calls */
		#define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE ( 732+23) / "" Disable Speculative Store Bypass. */
		@@ -238,6 +238,7 @@
		#define X86_FEATURE_VMW_VMMCALL ( 832+19) / "" VMware prefers VMMCALL hypercall instruction */
		#define X86_FEATURE_PVUNLOCK ( 832+20) / "" PV unlock function */
		#define X86_FEATURE_VCPUPREEMPT ( 832+21) / "" PV vcpu_is_preempted function */
		#define X86_FEATURE_TDX_GUEST ( 832+22) / Intel Trust Domain Extensions Guest */

		/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
		#define X86_FEATURE_FSGSBASE ( 932+ 0) / RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
		@@ -315,6 +316,7 @@
		#define X86_FEATURE_VIRT_SSBD (1332+25) / Virtualized Speculative Store Bypass Disable */
		#define X86_FEATURE_AMD_SSB_NO (1332+26) / "" Speculative Store Bypass is fixed in hardware. */
		#define X86_FEATURE_CPPC (1332+27) / Collaborative Processor Performance Control */
		#define X86_FEATURE_BRS (1332+31) / Branch Sampling available */

		/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
		#define X86_FEATURE_DTHERM (1432+ 0) / Digital Thermal Sensor */
		@@ -405,6 +407,7 @@
		#define X86_FEATURE_SEV (1932+ 1) / AMD Secure Encrypted Virtualization */
		#define X86_FEATURE_VM_PAGE_FLUSH (1932+ 2) / "" VM Page Flush MSR is supported */
		#define X86_FEATURE_SEV_ES (1932+ 3) / AMD Secure Encrypted Virtualization - Encrypted State */
		#define X86_FEATURE_V_TSC_AUX (1932+ 9) / "" Virtual TSC_AUX */
		#define X86_FEATURE_SME_COHERENT (1932+10) / "" AMD hardware-enforced cache coherency */

		/*