Commit 891e465a authored by Smita Koralahalli's avatar Smita Koralahalli Committed by Borislav Petkov
Browse files

x86/mce: Check whether writes to MCA_STATUS are getting ignored 

The platform can sometimes - depending on its settings - cause writes
to MCA_STATUS MSRs to get ignored, regardless of HWCR[McStatusWrEn]'s
value.

For further info see

  PPR for AMD Family 19h, Model 01h, Revision B1 Processors, doc ID 55898

at https://bugzilla.kernel.org/show_bug.cgi?id=206537

.

Therefore, probe for ignored writes to MCA_STATUS to determine if hardware
error injection is at all possible.

  [ bp: Heavily massage commit message and patch. ]

Signed-off-by: default avatarSmita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220214233640.70510-2-Smita.KoralahalliChannabasappa@amd.com
parent a111daf0

arch/x86/kernel/cpu/mce/inject.c

+47 −0
Original line number Diff line number Diff line
@@ -33,6 +33,8 @@ 


#include "internal.h"



static bool hw_injection_possible = true;



/*

 * Collect all the MCi_XXX settings

 */
@@ -339,6 +341,8 @@ static int __set_inj(const char *buf) 


	for (i = 0; i < N_INJ_TYPES; i++) {

		if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) {

			if (i > SW_INJ && !hw_injection_possible)

				continue;

			inj_type = i;

			return 0;

		}
@@ -717,11 +721,54 @@ static void __init debugfs_init(void) 
				    &i_mce, dfs_fls[i].fops);

}



static void check_hw_inj_possible(void)

{

	int cpu;

	u8 bank;



	/*

	 * This behavior exists only on SMCA systems though its not directly

	 * related to SMCA.

	 */

	if (!cpu_feature_enabled(X86_FEATURE_SMCA))

		return;



	cpu = get_cpu();



	for (bank = 0; bank < MAX_NR_BANKS; ++bank) {

		u64 status = MCI_STATUS_VAL, ipid;



		/* Check whether bank is populated */

		rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), ipid);

		if (!ipid)

			continue;



		toggle_hw_mce_inject(cpu, true);



		wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), status);

		rdmsrl_safe(mca_msr_reg(bank, MCA_STATUS), &status);



		if (!status) {

			hw_injection_possible = false;

			pr_warn("Platform does not allow *hardware* error injection."

				"Try using APEI EINJ instead.\n");

		}



		toggle_hw_mce_inject(cpu, false);



		break;

	}



	put_cpu();

}



static int __init inject_init(void)

{

	if (!alloc_cpumask_var(&mce_inject_cpumask, GFP_KERNEL))

		return -ENOMEM;



	check_hw_inj_possible();



	debugfs_init();



	register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify");

arch/x86/kernel/cpu/mce/internal.h

+1 −1
Original line number Diff line number Diff line
@@ -211,7 +211,7 @@ noinstr u64 mce_rdmsrl(u32 msr); 


static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg)

{

	if (mce_flags.smca) {

	if (cpu_feature_enabled(X86_FEATURE_SMCA)) {

		switch (reg) {

		case MCA_CTL:	 return MSR_AMD64_SMCA_MCx_CTL(bank);

		case MCA_ADDR:	 return MSR_AMD64_SMCA_MCx_ADDR(bank);