Loading drivers/edac/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -263,6 +263,7 @@ config EDAC_I10NM config EDAC_PND2 tristate "Intel Pondicherry2" depends on PCI && X86_64 && X86_MCE_INTEL select P2SB if X86 help Support for error detection and correction on the Intel Pondicherry2 Integrated Memory Controller. This SoC IP is Loading drivers/edac/pnd2_edac.c +20 −42 Original line number Diff line number Diff line Loading @@ -28,6 +28,8 @@ #include <linux/bitmap.h> #include <linux/math64.h> #include <linux/mod_devicetable.h> #include <linux/platform_data/x86/p2sb.h> #include <asm/cpu_device_id.h> #include <asm/intel-family.h> #include <asm/processor.h> Loading Loading @@ -232,42 +234,14 @@ static u64 get_mem_ctrl_hub_base_addr(void) return U64_LSHIFT(hi.base, 32) | U64_LSHIFT(lo.base, 15); } static u64 get_sideband_reg_base_addr(void) { struct pci_dev *pdev; u32 hi, lo; u8 hidden; pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x19dd, NULL); if (pdev) { /* Unhide the P2SB device, if it's hidden */ pci_read_config_byte(pdev, 0xe1, &hidden); if (hidden) pci_write_config_byte(pdev, 0xe1, 0); pci_read_config_dword(pdev, 0x10, &lo); pci_read_config_dword(pdev, 0x14, &hi); lo &= 0xfffffff0; /* Hide the P2SB device, if it was hidden before */ if (hidden) pci_write_config_byte(pdev, 0xe1, hidden); pci_dev_put(pdev); return (U64_LSHIFT(hi, 32) | U64_LSHIFT(lo, 0)); } else { return 0xfd000000; } } #define DNV_MCHBAR_SIZE 0x8000 #define DNV_SB_PORT_SIZE 0x10000 static int dnv_rd_reg(int port, int off, int op, void *data, size_t sz, char *name) { struct pci_dev *pdev; char *base; u64 addr; unsigned long size; void __iomem *base; struct resource r; int ret; if (op == 4) { pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x1980, NULL); Loading @@ -279,26 +253,30 @@ static int dnv_rd_reg(int port, int off, int op, void *data, size_t sz, char *na } else { /* MMIO via memory controller hub base address */ if (op == 0 && port == 0x4c) { addr = get_mem_ctrl_hub_base_addr(); if (!addr) memset(&r, 0, sizeof(r)); r.start = get_mem_ctrl_hub_base_addr(); if (!r.start) return -ENODEV; size = DNV_MCHBAR_SIZE; r.end = r.start + DNV_MCHBAR_SIZE - 1; } else { /* MMIO via sideband register base address */ addr = get_sideband_reg_base_addr(); if (!addr) return -ENODEV; addr += (port << 16); size = DNV_SB_PORT_SIZE; ret = p2sb_bar(NULL, 0, &r); if (ret) return ret; r.start += (port << 16); r.end = r.start + DNV_SB_PORT_SIZE - 1; } base = ioremap((resource_size_t)addr, size); base = ioremap(r.start, resource_size(&r)); if (!base) return -ENODEV; if (sz == 8) *(u32 *)(data + 4) = *(u32 *)(base + off + 4); *(u32 *)data = *(u32 *)(base + off); *(u64 *)data = readq(base + off); else *(u32 *)data = readl(base + off); iounmap(base); } Loading drivers/i2c/busses/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -108,6 +108,7 @@ config I2C_HIX5HD2 config I2C_I801 tristate "Intel 82801 (ICH/PCH)" depends on PCI select P2SB if X86 select CHECK_SIGNATURE if X86 && DMI select I2C_SMBUS help Loading drivers/i2c/busses/i2c-i801.c +9 −30 Original line number Diff line number Diff line Loading @@ -111,6 +111,7 @@ #include <linux/err.h> #include <linux/platform_device.h> #include <linux/platform_data/itco_wdt.h> #include <linux/platform_data/x86/p2sb.h> #include <linux/pm_runtime.h> #include <linux/mutex.h> Loading Loading @@ -140,7 +141,6 @@ #define TCOBASE 0x050 #define TCOCTL 0x054 #define SBREG_BAR 0x10 #define SBREG_SMBCTRL 0xc6000c #define SBREG_SMBCTRL_DNV 0xcf000c Loading Loading @@ -1482,45 +1482,24 @@ i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, .version = 4, }; struct resource *res; unsigned int devfn; u64 base64_addr; u32 base_addr; u8 hidden; int ret; /* * We must access the NO_REBOOT bit over the Primary to Sideband * bridge (P2SB). The BIOS prevents the P2SB device from being * enumerated by the PCI subsystem, so we need to unhide/hide it * to lookup the P2SB BAR. * (P2SB) bridge. */ pci_lock_rescan_remove(); devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); /* Unhide the P2SB device, if it is hidden */ pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); if (hidden) pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); base64_addr = base_addr & 0xfffffff0; pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); base64_addr |= (u64)base_addr << 32; /* Hide the P2SB device, if it was hidden before */ if (hidden) pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); pci_unlock_rescan_remove(); res = &tco_res[1]; ret = p2sb_bar(pci_dev->bus, 0, res); if (ret) return ERR_PTR(ret); if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; res->start += SBREG_SMBCTRL_DNV; else res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; res->start += SBREG_SMBCTRL; res->end = res->start + 3; res->flags = IORESOURCE_MEM; return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, tco_res, 2, &pldata, sizeof(pldata)); Loading drivers/leds/simple/Kconfig +3 −3 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0-only config LEDS_SIEMENS_SIMATIC_IPC tristate "LED driver for Siemens Simatic IPCs" depends on LEDS_CLASS depends on LEDS_GPIO depends on SIEMENS_SIMATIC_IPC help This option enables support for the LEDs of several Industrial PCs from Siemens. To compile this driver as a module, choose M here: the module will be called simatic-ipc-leds. To compile this driver as a module, choose M here: the modules will be called simatic-ipc-leds and simatic-ipc-leds-gpio. Loading
drivers/edac/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -263,6 +263,7 @@ config EDAC_I10NM config EDAC_PND2 tristate "Intel Pondicherry2" depends on PCI && X86_64 && X86_MCE_INTEL select P2SB if X86 help Support for error detection and correction on the Intel Pondicherry2 Integrated Memory Controller. This SoC IP is Loading
drivers/edac/pnd2_edac.c +20 −42 Original line number Diff line number Diff line Loading @@ -28,6 +28,8 @@ #include <linux/bitmap.h> #include <linux/math64.h> #include <linux/mod_devicetable.h> #include <linux/platform_data/x86/p2sb.h> #include <asm/cpu_device_id.h> #include <asm/intel-family.h> #include <asm/processor.h> Loading Loading @@ -232,42 +234,14 @@ static u64 get_mem_ctrl_hub_base_addr(void) return U64_LSHIFT(hi.base, 32) | U64_LSHIFT(lo.base, 15); } static u64 get_sideband_reg_base_addr(void) { struct pci_dev *pdev; u32 hi, lo; u8 hidden; pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x19dd, NULL); if (pdev) { /* Unhide the P2SB device, if it's hidden */ pci_read_config_byte(pdev, 0xe1, &hidden); if (hidden) pci_write_config_byte(pdev, 0xe1, 0); pci_read_config_dword(pdev, 0x10, &lo); pci_read_config_dword(pdev, 0x14, &hi); lo &= 0xfffffff0; /* Hide the P2SB device, if it was hidden before */ if (hidden) pci_write_config_byte(pdev, 0xe1, hidden); pci_dev_put(pdev); return (U64_LSHIFT(hi, 32) | U64_LSHIFT(lo, 0)); } else { return 0xfd000000; } } #define DNV_MCHBAR_SIZE 0x8000 #define DNV_SB_PORT_SIZE 0x10000 static int dnv_rd_reg(int port, int off, int op, void *data, size_t sz, char *name) { struct pci_dev *pdev; char *base; u64 addr; unsigned long size; void __iomem *base; struct resource r; int ret; if (op == 4) { pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x1980, NULL); Loading @@ -279,26 +253,30 @@ static int dnv_rd_reg(int port, int off, int op, void *data, size_t sz, char *na } else { /* MMIO via memory controller hub base address */ if (op == 0 && port == 0x4c) { addr = get_mem_ctrl_hub_base_addr(); if (!addr) memset(&r, 0, sizeof(r)); r.start = get_mem_ctrl_hub_base_addr(); if (!r.start) return -ENODEV; size = DNV_MCHBAR_SIZE; r.end = r.start + DNV_MCHBAR_SIZE - 1; } else { /* MMIO via sideband register base address */ addr = get_sideband_reg_base_addr(); if (!addr) return -ENODEV; addr += (port << 16); size = DNV_SB_PORT_SIZE; ret = p2sb_bar(NULL, 0, &r); if (ret) return ret; r.start += (port << 16); r.end = r.start + DNV_SB_PORT_SIZE - 1; } base = ioremap((resource_size_t)addr, size); base = ioremap(r.start, resource_size(&r)); if (!base) return -ENODEV; if (sz == 8) *(u32 *)(data + 4) = *(u32 *)(base + off + 4); *(u32 *)data = *(u32 *)(base + off); *(u64 *)data = readq(base + off); else *(u32 *)data = readl(base + off); iounmap(base); } Loading
drivers/i2c/busses/Kconfig +1 −0 Original line number Diff line number Diff line Loading @@ -108,6 +108,7 @@ config I2C_HIX5HD2 config I2C_I801 tristate "Intel 82801 (ICH/PCH)" depends on PCI select P2SB if X86 select CHECK_SIGNATURE if X86 && DMI select I2C_SMBUS help Loading
drivers/i2c/busses/i2c-i801.c +9 −30 Original line number Diff line number Diff line Loading @@ -111,6 +111,7 @@ #include <linux/err.h> #include <linux/platform_device.h> #include <linux/platform_data/itco_wdt.h> #include <linux/platform_data/x86/p2sb.h> #include <linux/pm_runtime.h> #include <linux/mutex.h> Loading Loading @@ -140,7 +141,6 @@ #define TCOBASE 0x050 #define TCOCTL 0x054 #define SBREG_BAR 0x10 #define SBREG_SMBCTRL 0xc6000c #define SBREG_SMBCTRL_DNV 0xcf000c Loading Loading @@ -1482,45 +1482,24 @@ i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, .version = 4, }; struct resource *res; unsigned int devfn; u64 base64_addr; u32 base_addr; u8 hidden; int ret; /* * We must access the NO_REBOOT bit over the Primary to Sideband * bridge (P2SB). The BIOS prevents the P2SB device from being * enumerated by the PCI subsystem, so we need to unhide/hide it * to lookup the P2SB BAR. * (P2SB) bridge. */ pci_lock_rescan_remove(); devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); /* Unhide the P2SB device, if it is hidden */ pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); if (hidden) pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); base64_addr = base_addr & 0xfffffff0; pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); base64_addr |= (u64)base_addr << 32; /* Hide the P2SB device, if it was hidden before */ if (hidden) pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); pci_unlock_rescan_remove(); res = &tco_res[1]; ret = p2sb_bar(pci_dev->bus, 0, res); if (ret) return ERR_PTR(ret); if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; res->start += SBREG_SMBCTRL_DNV; else res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; res->start += SBREG_SMBCTRL; res->end = res->start + 3; res->flags = IORESOURCE_MEM; return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, tco_res, 2, &pldata, sizeof(pldata)); Loading
drivers/leds/simple/Kconfig +3 −3 Original line number Diff line number Diff line # SPDX-License-Identifier: GPL-2.0-only config LEDS_SIEMENS_SIMATIC_IPC tristate "LED driver for Siemens Simatic IPCs" depends on LEDS_CLASS depends on LEDS_GPIO depends on SIEMENS_SIMATIC_IPC help This option enables support for the LEDs of several Industrial PCs from Siemens. To compile this driver as a module, choose M here: the module will be called simatic-ipc-leds. To compile this driver as a module, choose M here: the modules will be called simatic-ipc-leds and simatic-ipc-leds-gpio.