Unverified Commit 88dde5e2 authored by Andre Przywara's avatar Andre Przywara Committed by Maxime Ripard
Browse files

clk: sunxi-ng: Add support for the Allwinner H616 CCU 



While the clocks are fairly similar to the H6, many differ in tiny
details, so a separate clock driver seems indicated.

Derived from the H6 clock driver, and adjusted according to the manual.

Signed-off-by: default avatarAndre Przywara <andre.przywara@arm.com>
Acked-by: default avatarMaxime Ripard <mripard@kernel.org>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20210127172500.13356-4-andre.przywara@arm.com
parent 394a36dd

drivers/clk/sunxi-ng/Kconfig

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@@ -32,6 +32,11 @@ config SUN50I_H6_CCU 
	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST



config SUN50I_H616_CCU

	bool "Support for the Allwinner H616 CCU"

	default ARM64 && ARCH_SUNXI

	depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST



config SUN50I_H6_R_CCU

	bool "Support for the Allwinner H6 and H616 PRCM CCU"

	default ARM64 && ARCH_SUNXI

drivers/clk/sunxi-ng/Makefile

+1 −0
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@@ -26,6 +26,7 @@ obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o 
obj-$(CONFIG_SUN50I_A100_CCU)	+= ccu-sun50i-a100.o

obj-$(CONFIG_SUN50I_A100_R_CCU)	+= ccu-sun50i-a100-r.o

obj-$(CONFIG_SUN50I_H6_CCU)	+= ccu-sun50i-h6.o

obj-$(CONFIG_SUN50I_H616_CCU)	+= ccu-sun50i-h616.o

obj-$(CONFIG_SUN50I_H6_R_CCU)	+= ccu-sun50i-h6-r.o

obj-$(CONFIG_SUN4I_A10_CCU)	+= ccu-sun4i-a10.o

obj-$(CONFIG_SUN5I_CCU)		+= ccu-sun5i.o

drivers/clk/sunxi-ng/ccu-sun50i-h616.c

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File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/sunxi-ng/ccu-sun50i-h616.h

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/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright 2020 Arm Ltd.

 */



#ifndef _CCU_SUN50I_H616_H_

#define _CCU_SUN50I_H616_H_



#include <dt-bindings/clock/sun50i-h616-ccu.h>

#include <dt-bindings/reset/sun50i-h616-ccu.h>



#define CLK_OSC12M		0

#define CLK_PLL_CPUX		1

#define CLK_PLL_DDR0		2

#define CLK_PLL_DDR1		3



/* PLL_PERIPH0 exported for PRCM */



#define CLK_PLL_PERIPH0_2X	5

#define CLK_PLL_PERIPH1		6

#define CLK_PLL_PERIPH1_2X	7

#define CLK_PLL_GPU		8

#define CLK_PLL_VIDEO0		9

#define CLK_PLL_VIDEO0_4X	10

#define CLK_PLL_VIDEO1		11

#define CLK_PLL_VIDEO1_4X	12

#define CLK_PLL_VIDEO2		13

#define CLK_PLL_VIDEO2_4X	14

#define CLK_PLL_VE		15

#define CLK_PLL_DE		16

#define CLK_PLL_AUDIO_HS	17

#define CLK_PLL_AUDIO_1X	18

#define CLK_PLL_AUDIO_2X	19

#define CLK_PLL_AUDIO_4X	20



/* CPUX clock exported for DVFS */



#define CLK_AXI			22

#define CLK_CPUX_APB		23

#define CLK_PSI_AHB1_AHB2	24

#define CLK_AHB3		25



/* APB1 clock exported for PIO */



#define CLK_APB2		27

#define CLK_MBUS		28



/* All module clocks and bus gates are exported except DRAM */



#define CLK_DRAM		49



#define CLK_BUS_DRAM		56



#define CLK_NUMBER		(CLK_BUS_HDCP + 1)



#endif /* _CCU_SUN50I_H616_H_ */

include/dt-bindings/clock/sun50i-h616-ccu.h

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/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */

/*

 * Copyright (C) 2020 Arm Ltd.

 */



#ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_

#define _DT_BINDINGS_CLK_SUN50I_H616_H_



#define CLK_PLL_PERIPH0		4



#define CLK_CPUX		21



#define CLK_APB1		26



#define CLK_DE			29

#define CLK_BUS_DE		30

#define CLK_DEINTERLACE		31

#define CLK_BUS_DEINTERLACE	32

#define CLK_G2D			33

#define CLK_BUS_G2D		34

#define CLK_GPU0		35

#define CLK_BUS_GPU		36

#define CLK_GPU1		37

#define CLK_CE			38

#define CLK_BUS_CE		39

#define CLK_VE			40

#define CLK_BUS_VE		41

#define CLK_BUS_DMA		42

#define CLK_BUS_HSTIMER		43

#define CLK_AVS			44

#define CLK_BUS_DBG		45

#define CLK_BUS_PSI		46

#define CLK_BUS_PWM		47

#define CLK_BUS_IOMMU		48



#define CLK_MBUS_DMA		50

#define CLK_MBUS_VE		51

#define CLK_MBUS_CE		52

#define CLK_MBUS_TS		53

#define CLK_MBUS_NAND		54

#define CLK_MBUS_G2D		55



#define CLK_NAND0		57

#define CLK_NAND1		58

#define CLK_BUS_NAND		59

#define CLK_MMC0		60

#define CLK_MMC1		61

#define CLK_MMC2		62

#define CLK_BUS_MMC0		63

#define CLK_BUS_MMC1		64

#define CLK_BUS_MMC2		65

#define CLK_BUS_UART0		66

#define CLK_BUS_UART1		67

#define CLK_BUS_UART2		68

#define CLK_BUS_UART3		69

#define CLK_BUS_UART4		70

#define CLK_BUS_UART5		71

#define CLK_BUS_I2C0		72

#define CLK_BUS_I2C1		73

#define CLK_BUS_I2C2		74

#define CLK_BUS_I2C3		75

#define CLK_BUS_I2C4		76

#define CLK_SPI0		77

#define CLK_SPI1		78

#define CLK_BUS_SPI0		79

#define CLK_BUS_SPI1		80

#define CLK_EMAC_25M		81

#define CLK_BUS_EMAC0		82

#define CLK_BUS_EMAC1		83

#define CLK_TS			84

#define CLK_BUS_TS		85

#define CLK_BUS_THS		86

#define CLK_SPDIF		87

#define CLK_BUS_SPDIF		88

#define CLK_DMIC		89

#define CLK_BUS_DMIC		90

#define CLK_AUDIO_CODEC_1X	91

#define CLK_AUDIO_CODEC_4X	92

#define CLK_BUS_AUDIO_CODEC	93

#define CLK_AUDIO_HUB		94

#define CLK_BUS_AUDIO_HUB	95

#define CLK_USB_OHCI0		96

#define CLK_USB_PHY0		97

#define CLK_USB_OHCI1		98

#define CLK_USB_PHY1		99

#define CLK_USB_OHCI2		100

#define CLK_USB_PHY2		101

#define CLK_USB_OHCI3		102

#define CLK_USB_PHY3		103

#define CLK_BUS_OHCI0		104

#define CLK_BUS_OHCI1		105

#define CLK_BUS_OHCI2		106

#define CLK_BUS_OHCI3		107

#define CLK_BUS_EHCI0		108

#define CLK_BUS_EHCI1		109

#define CLK_BUS_EHCI2		110

#define CLK_BUS_EHCI3		111

#define CLK_BUS_OTG		112

#define CLK_BUS_KEYADC		113

#define CLK_HDMI		114

#define CLK_HDMI_SLOW		115

#define CLK_HDMI_CEC		116

#define CLK_BUS_HDMI		117

#define CLK_BUS_TCON_TOP	118

#define CLK_TCON_TV0		119

#define CLK_TCON_TV1		120

#define CLK_BUS_TCON_TV0	121

#define CLK_BUS_TCON_TV1	122

#define CLK_TVE0		123

#define CLK_BUS_TVE_TOP		124

#define CLK_BUS_TVE0		125

#define CLK_HDCP		126

#define CLK_BUS_HDCP		127



#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */