Commit 88d4cea2 authored by Chris Park's avatar Chris Park Committed by Alex Deucher
Browse files

drm/amd/display: Port DCN30 420 logic to DCN32 



[Why]
420 modes are limited by FMT buffer width of 4096
which requires multi-pipe support in form of ODM
combine.  If 420 modes have greater HActive than
4096, the DML logic should accomodate whether
it should be rejected, or ODM combine 2:1 or 4:1
is triggered accordingly.

[How]
FMT Buffer limit of 4096 in DCN32. Force ODM
combine depending on HActive and FMT Buffer limit.
Reject modes if TMDS 420 and above 4096.

Acked-by: default avatarWayne Lin <wayne.lin@amd.com>
Signed-off-by: default avatarChris Park <chris.park@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 37a0bad6

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c

+2 −0
Original line number Diff line number Diff line
@@ -1992,6 +1992,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
				dml32_CalculateODMMode(

						mode_lib->vba.MaximumPixelsPerLinePerDSCUnit,

						mode_lib->vba.HActive[k],

						mode_lib->vba.OutputFormat[k],

						mode_lib->vba.Output[k],

						mode_lib->vba.ODMUse[k],

						mode_lib->vba.MaxDispclk[i],
@@ -2013,6 +2014,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l 
				dml32_CalculateODMMode(

						mode_lib->vba.MaximumPixelsPerLinePerDSCUnit,

						mode_lib->vba.HActive[k],

						mode_lib->vba.OutputFormat[k],

						mode_lib->vba.Output[k],

						mode_lib->vba.ODMUse[k],

						mode_lib->vba.MaxDispclk[i],

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c

+26 −0
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ 
#include "display_mode_vba_32.h"

#include "../display_mode_lib.h"



#define DCN32_MAX_FMT_420_BUFFER_WIDTH 4096



unsigned int dml32_dscceComputeDelay(

		unsigned int bpc,

		double BPP,
@@ -1182,6 +1184,7 @@ void dml32_CalculateDETBufferSize( 
void dml32_CalculateODMMode(

		unsigned int MaximumPixelsPerLinePerDSCUnit,

		unsigned int HActive,

		enum output_format_class OutFormat,

		enum output_encoder_class Output,

		enum odm_combine_policy ODMUse,

		double StateDispclk,
@@ -1253,6 +1256,29 @@ void dml32_CalculateODMMode( 
		else

			*TotalAvailablePipesSupport = false;

	}

	if (OutFormat == dm_420 && HActive > DCN32_MAX_FMT_420_BUFFER_WIDTH &&

			ODMUse != dm_odm_combine_policy_4to1) {

		if (HActive > DCN32_MAX_FMT_420_BUFFER_WIDTH * 4) {

			*ODMMode = dm_odm_combine_mode_disabled;

			*NumberOfDPP = 0;

			*TotalAvailablePipesSupport = false;

		} else if (HActive > DCN32_MAX_FMT_420_BUFFER_WIDTH * 2 ||

				*ODMMode == dm_odm_combine_mode_4to1) {

			*ODMMode = dm_odm_combine_mode_4to1;

			*RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineFourToOne;

			*NumberOfDPP = 4;

		} else {

			*ODMMode = dm_odm_combine_mode_2to1;

			*RequiredDISPCLKPerSurface = SurfaceRequiredDISPCLKWithODMCombineTwoToOne;

			*NumberOfDPP = 2;

		}

	}

	if (Output == dm_hdmi && OutFormat == dm_420 &&

			HActive > DCN32_MAX_FMT_420_BUFFER_WIDTH) {

		*ODMMode = dm_odm_combine_mode_disabled;

		*NumberOfDPP = 0;

		*TotalAvailablePipesSupport = false;

	}

}



double dml32_CalculateRequiredDispclk(

drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.h

+1 −0
Original line number Diff line number Diff line
@@ -216,6 +216,7 @@ void dml32_CalculateDETBufferSize( 
void dml32_CalculateODMMode(

		unsigned int MaximumPixelsPerLinePerDSCUnit,

		unsigned int HActive,

		enum output_format_class OutFormat,

		enum output_encoder_class Output,

		enum odm_combine_policy ODMUse,

		double StateDispclk,