Commit 88d23eda authored by Ramalingam C's avatar Ramalingam C
Browse files

drm/i915/dg2: Add Wa_22011450934 



An indirect ctx wabb is implemented as per Wa_22011450934 to avoid rcs
restore hang during context restore of a preempted context in GPGPU mode

Signed-off-by: default avatarRamalingam C <ramalingam.c@intel.com>
cc: Chris Wilson <chris.p.wilson@intel.com>
Reviewed-by: default avatarMatthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220128185209.18077-2-ramalingam.c@intel.com
parent ba2c5d15

drivers/gpu/drm/i915/gt/intel_lrc.c

+28 −0
Original line number Diff line number Diff line
@@ -1164,6 +1164,29 @@ gen12_emit_cmd_buf_wa(const struct intel_context *ce, u32 *cs) 
	return cs;

}



/*

 * On DG2 during context restore of a preempted context in GPGPU mode,

 * RCS restore hang is detected. This is extremely timing dependent.

 * To address this below sw wabb is implemented for DG2 A steppings.

 */

static u32 *

dg2_emit_rcs_hang_wabb(const struct intel_context *ce, u32 *cs)

{

	*cs++ = MI_LOAD_REGISTER_IMM(1);

	*cs++ = i915_mmio_reg_offset(GEN12_STATE_ACK_DEBUG);

	*cs++ = 0x21;



	*cs++ = MI_LOAD_REGISTER_REG;

	*cs++ = i915_mmio_reg_offset(RING_NOPID(ce->engine->mmio_base));

	*cs++ = i915_mmio_reg_offset(GEN12_CULLBIT1);



	*cs++ = MI_LOAD_REGISTER_REG;

	*cs++ = i915_mmio_reg_offset(RING_NOPID(ce->engine->mmio_base));

	*cs++ = i915_mmio_reg_offset(GEN12_CULLBIT2);



	return cs;

}



static u32 *

gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)

{
@@ -1171,6 +1194,11 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) 
	cs = gen12_emit_cmd_buf_wa(ce, cs);

	cs = gen12_emit_restore_scratch(ce, cs);



	/* Wa_22011450934:dg2 */

	if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_A0, STEP_B0) ||

	    IS_DG2_GRAPHICS_STEP(ce->engine->i915, G11, STEP_A0, STEP_B0))

		cs = dg2_emit_rcs_hang_wabb(ce, cs);



	/* Wa_16013000631:dg2 */

	if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) ||

	    IS_DG2_G11(ce->engine->i915))

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -13024,4 +13024,8 @@ enum skl_power_gate { 
#define SLICE_COMMON_ECO_CHICKEN1		_MMIO(0x731C)

#define   MSC_MSAA_REODER_BUF_BYPASS_DISABLE	REG_BIT(14)









#define GEN12_CULLBIT1			_MMIO(0x6100)









#define GEN12_CULLBIT2			_MMIO(0x7030)









#define GEN12_STATE_ACK_DEBUG		_MMIO(0x20BC)

















#endif /* _I915_REG_H_ */