Commit 88b31f07 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:

 - Spectre/Meltdown safelisting for some Qualcomm KRYO cores

 - Fix RCU splat when failing to online a CPU due to a feature mismatch

 - Fix a recently introduced sparse warning in kexec()

 - Fix handling of CPU erratum 1418040 for late CPUs

 - Ensure hot-added memory falls within linear-mapped region

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: cpu_errata: Apply Erratum 845719 to KRYO2XX Silver
  arm64: proton-pack: Add KRYO2XX silver CPUs to spectre-v2 safe-list
  arm64: kpti: Add KRYO2XX gold/silver CPU cores to kpti safelist
  arm64: Add MIDR value for KRYO2XX gold/silver CPU cores
  arm64/mm: Validate hotplug range before creating linear mapping
  arm64: smp: Tell RCU about CPUs that fail to come online
  arm64: psci: Avoid printing in cpu_psci_cpu_die()
  arm64: kexec_file: Fix sparse warning
  arm64: errata: Fix handling of 1418040 with late CPU onlining
parents d3ba7afc 23c21641

arch/arm64/include/asm/cpufeature.h

+2 −0
Original line number Diff line number Diff line
@@ -268,6 +268,8 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; 
/*

 * CPU feature detected at boot time based on feature of one or more CPUs.

 * All possible conflicts for a late CPU are ignored.

 * NOTE: this means that a late CPU with the feature will *not* cause the

 * capability to be advertised by cpus_have_*cap()!

 */

#define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE		\

	(ARM64_CPUCAP_SCOPE_LOCAL_CPU		|	\

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -86,6 +86,8 @@ 
#define QCOM_CPU_PART_FALKOR_V1		0x800

#define QCOM_CPU_PART_FALKOR		0xC00

#define QCOM_CPU_PART_KRYO		0x200

#define QCOM_CPU_PART_KRYO_2XX_GOLD	0x800

#define QCOM_CPU_PART_KRYO_2XX_SILVER	0x801

#define QCOM_CPU_PART_KRYO_3XX_SILVER	0x803

#define QCOM_CPU_PART_KRYO_4XX_GOLD	0x804

#define QCOM_CPU_PART_KRYO_4XX_SILVER	0x805
@@ -116,6 +118,8 @@ 
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)

#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR)

#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)

#define MIDR_QCOM_KRYO_2XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_GOLD)

#define MIDR_QCOM_KRYO_2XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_2XX_SILVER)

#define MIDR_QCOM_KRYO_3XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_3XX_SILVER)

#define MIDR_QCOM_KRYO_4XX_GOLD MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_GOLD)

#define MIDR_QCOM_KRYO_4XX_SILVER MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO_4XX_SILVER)

arch/arm64/kernel/cpu_errata.c

+2 −0
Original line number Diff line number Diff line
@@ -299,6 +299,8 @@ static const struct midr_range erratum_845719_list[] = { 
	MIDR_REV_RANGE(MIDR_CORTEX_A53, 0, 0, 4),

	/* Brahma-B53 r0p[0] */

	MIDR_REV(MIDR_BRAHMA_B53, 0, 0),

	/* Kryo2XX Silver rAp4 */

	MIDR_REV(MIDR_QCOM_KRYO_2XX_SILVER, 0xa, 0x4),

	{},

};

#endif

arch/arm64/kernel/cpufeature.c

+2 −0
Original line number Diff line number Diff line
@@ -1337,6 +1337,8 @@ static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 
		MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),

		MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),

		MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),

		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD),

		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER),

		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER),

		MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER),

		{ /* sentinel */ }

arch/arm64/kernel/kexec_image.c

+1 −1
Original line number Diff line number Diff line
@@ -127,7 +127,7 @@ static void *image_load(struct kimage *image, 
				kernel_segment->mem, kbuf.bufsz,

				kernel_segment->memsz);



	return 0;

	return NULL;

}



#ifdef CONFIG_KEXEC_IMAGE_VERIFY_SIG