Commit 88a15179 authored by Adrien Grassein's avatar Adrien Grassein Committed by Shawn Guo
Browse files

arm64: dts: imx8mm-nitrogen-r2: add UARTs 



Add description and pin muxing for UARTs.

Signed-off-by: default avatarAdrien Grassein <adrien.grassein@gmail.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 421f715c

arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts

+48 −0
Original line number Diff line number Diff line
@@ -198,6 +198,14 @@ 
	};

};



/* BT */

&uart1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart1>;

	uart-has-rtscts;

	status = "okay";

};



/* console */

&uart2 {

	pinctrl-names = "default";
@@ -207,6 +215,21 @@ 
	status = "okay";

};



/* J15 */

&uart3 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart3>;

	uart-has-rtscts;

	status = "okay";

};



/* J9 */

&uart4 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_uart4>;

	status = "okay";

};



/* eMMC */

&usdhc1 {

	bus-width = <8>;
@@ -339,6 +362,15 @@ 
		>;

	};



	pinctrl_uart1: uart1grp {

		fsl,pins = <

			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140

			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140

			MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140

			MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140

		>;

	};



	pinctrl_uart2: uart2grp {

		fsl,pins = <

			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
@@ -346,6 +378,22 @@ 
		>;

	};



	pinctrl_uart3: uart3grp {

		fsl,pins = <

			MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140

			MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140

			MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140

			MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140

		>;

	};



	pinctrl_uart4: uart4grp {

		fsl,pins = <

			MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140

			MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140

		>;

	};



	pinctrl_usbotg1: usbotg1grp {

		fsl,pins = <

			MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR	0x16