Commit 886e1387 authored by Vladimir Oltean's avatar Vladimir Oltean Committed by David S. Miller
Browse files

net: mscc: ocelot: convert QSYS_SWITCH_PORT_MODE and SYS_PORT_MODE to regfields 



Currently Felix and Ocelot share the same bit layout in these per-port
registers, but Seville does not. So we need reg_fields for that.

Actually since these are per-port registers, we need to also specify the
number of ports, and register size per port, and use the regmap API for
multiple ports.

There's a more subtle point to be made about the other 2 register
fields:
- QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG
- QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE
which we are not writing any longer, for 2 reasons:
- Using the previous API (ocelot_write_rix), we were only writing 1 for
  Felix and Ocelot, which was their hardware-default value, and which
  there wasn't any intention in changing.
- In the case of SCH_NEXT_CFG, in fact Seville does not have this
  register field at all, and therefore, if we want to have common code
  we would be required to not write to it.

Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2789658f

drivers/net/dsa/ocelot/felix.c

+3 −6
Original line number Diff line number Diff line
@@ -249,8 +249,7 @@ static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port, 
	struct ocelot_port *ocelot_port = ocelot->ports[port];



	ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG);

	ocelot_rmw_rix(ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,

		       QSYS_SWITCH_PORT_MODE, port);

	ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);

}



static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port,
@@ -326,10 +325,8 @@ static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port, 
			 ANA_PORT_PORT_CFG, port);



	/* Core: Enable port for frame transfer */

	ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |

			 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |

			 QSYS_SWITCH_PORT_MODE_PORT_ENA,

			 QSYS_SWITCH_PORT_MODE, port);

	ocelot_fields_write(ocelot, port,

			    QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);



	if (felix->info->pcs_link_up)

		felix->info->pcs_link_up(ocelot, port, link_an_mode, interface,

drivers/net/dsa/ocelot/felix_vsc9959.c

+11 −0
Original line number Diff line number Diff line
@@ -503,6 +503,17 @@ static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = { 
	[ANA_TABLES_MACTINDX_M_INDEX] = REG_FIELD(ANA_TABLES_MACTINDX, 0, 10),

	[SYS_RESET_CFG_CORE_ENA] = REG_FIELD(SYS_RESET_CFG, 0, 0),

	[GCB_SOFT_RST_SWC_RST] = REG_FIELD(GCB_SOFT_RST, 0, 0),

	/* Replicated per number of ports (7), register size 4 per port */

	[QSYS_SWITCH_PORT_MODE_PORT_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 14, 14, 7, 4),

	[QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 11, 13, 7, 4),

	[QSYS_SWITCH_PORT_MODE_YEL_RSRVD] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 10, 10, 7, 4),

	[QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 9, 9, 7, 4),

	[QSYS_SWITCH_PORT_MODE_TX_PFC_ENA] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 1, 8, 7, 4),

	[QSYS_SWITCH_PORT_MODE_TX_PFC_MODE] = REG_FIELD_ID(QSYS_SWITCH_PORT_MODE, 0, 0, 7, 4),

	[SYS_PORT_MODE_DATA_WO_TS] = REG_FIELD_ID(SYS_PORT_MODE, 5, 6, 7, 4),

	[SYS_PORT_MODE_INCL_INJ_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 3, 4, 7, 4),

	[SYS_PORT_MODE_INCL_XTR_HDR] = REG_FIELD_ID(SYS_PORT_MODE, 1, 2, 7, 4),

	[SYS_PORT_MODE_INCL_HDR_ERR] = REG_FIELD_ID(SYS_PORT_MODE, 0, 0, 7, 4),

};



static const struct ocelot_stat_layout vsc9959_stats_layout[] = {

drivers/net/ethernet/mscc/ocelot.c

+14 −22
Original line number Diff line number Diff line
@@ -389,10 +389,8 @@ void ocelot_adjust_link(struct ocelot *ocelot, int port, 
			 ANA_PFC_PFC_CFG, port);



	/* Core: Enable port for frame transfer */

	ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |

			 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |

			 QSYS_SWITCH_PORT_MODE_PORT_ENA,

			 QSYS_SWITCH_PORT_MODE, port);

	ocelot_fields_write(ocelot, port,

			    QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);



	/* Flow control */

	ocelot_write_rix(ocelot, SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
@@ -423,8 +421,7 @@ void ocelot_port_disable(struct ocelot *ocelot, int port) 
	struct ocelot_port *ocelot_port = ocelot->ports[port];



	ocelot_port_writel(ocelot_port, 0, DEV_MAC_ENA_CFG);

	ocelot_rmw_rix(ocelot, 0, QSYS_SWITCH_PORT_MODE_PORT_ENA,

		       QSYS_SWITCH_PORT_MODE, port);

	ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);

}

EXPORT_SYMBOL(ocelot_port_disable);
@@ -1392,27 +1389,22 @@ void ocelot_configure_cpu(struct ocelot *ocelot, int npi, 
			     QSYS_EXT_CPU_CFG);



		/* Enable NPI port */

		ocelot_write_rix(ocelot,

				 QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |

				 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |

				 QSYS_SWITCH_PORT_MODE_PORT_ENA,

				 QSYS_SWITCH_PORT_MODE, npi);

		ocelot_fields_write(ocelot, npi,

				    QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);

		/* NPI port Injection/Extraction configuration */

		ocelot_write_rix(ocelot,

				 SYS_PORT_MODE_INCL_XTR_HDR(extraction) |

				 SYS_PORT_MODE_INCL_INJ_HDR(injection),

				 SYS_PORT_MODE, npi);

		ocelot_fields_write(ocelot, npi, SYS_PORT_MODE_INCL_XTR_HDR,

				    extraction);

		ocelot_fields_write(ocelot, npi, SYS_PORT_MODE_INCL_INJ_HDR,

				    injection);

	}



	/* Enable CPU port module */

	ocelot_write_rix(ocelot, QSYS_SWITCH_PORT_MODE_INGRESS_DROP_MODE |

			 QSYS_SWITCH_PORT_MODE_SCH_NEXT_CFG(1) |

			 QSYS_SWITCH_PORT_MODE_PORT_ENA,

			 QSYS_SWITCH_PORT_MODE, cpu);

	ocelot_fields_write(ocelot, cpu, QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);

	/* CPU port Injection/Extraction configuration */

	ocelot_write_rix(ocelot, SYS_PORT_MODE_INCL_XTR_HDR(extraction) |

			 SYS_PORT_MODE_INCL_INJ_HDR(injection),

			 SYS_PORT_MODE, cpu);

	ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_XTR_HDR,

			    extraction);

	ocelot_fields_write(ocelot, cpu, SYS_PORT_MODE_INCL_INJ_HDR,

			    injection);



	/* Configure the CPU port to be VLAN aware */

	ocelot_write_gix(ocelot, ANA_PORT_VLAN_CFG_VLAN_VID(0) |

drivers/net/ethernet/mscc/ocelot.h

+0 −6
Original line number Diff line number Diff line
@@ -102,9 +102,6 @@ void ocelot_port_lag_leave(struct ocelot *ocelot, int port, 
u32 ocelot_port_readl(struct ocelot_port *port, u32 reg);

void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg);



#define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))

#define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))



int ocelot_probe_port(struct ocelot *ocelot, int port, struct regmap *target,

		      struct phy_device *phy);
@@ -116,7 +113,4 @@ extern struct notifier_block ocelot_netdevice_nb; 
extern struct notifier_block ocelot_switchdev_nb;

extern struct notifier_block ocelot_switchdev_blocking_nb;



#define ocelot_field_write(ocelot, reg, val) regmap_field_write((ocelot)->regfields[(reg)], (val))

#define ocelot_field_read(ocelot, reg, val) regmap_field_read((ocelot)->regfields[(reg)], (val))



#endif

drivers/net/ethernet/mscc/ocelot_io.c

+2 −0
Original line number Diff line number Diff line
@@ -89,6 +89,8 @@ int ocelot_regfields_init(struct ocelot *ocelot, 
		regfield.reg = ocelot->map[target][reg & REG_MASK];

		regfield.lsb = regfields[i].lsb;

		regfield.msb = regfields[i].msb;

		regfield.id_size = regfields[i].id_size;

		regfield.id_offset = regfields[i].id_offset;



		ocelot->regfields[i] =

		devm_regmap_field_alloc(ocelot->dev,