Commit 87cb6d80 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODE 



We have to specify in the Render Control Unit Mode register
when CCS is enabled.

v2:
 - Move RCU_MODE programming to a helper function.  (Tvrtko)
 - Clean up and clarify comments.  (Tvrtko)
 - Add RCU_MODE to the GuC save/restore list.  (Daniele)
v3:
 - Move this patch before the GuC ADS update to enable compute engines;
   the definition of RCU_MODE and its insertion into the save/restore
   list moves to this patch.  (Daniele)
v4:
 - Call xehp_enable_ccs_engines() directly in guc_resume() and
   execlists_resume() rather than adding an extra layer of wrapping to
   the engine->resume() vfunc.  (Umesh)

Bspec: 46034
Original-author: Michel Thierry
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
Cc: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Signed-off-by: default avatarDaniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: default avatarAravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarUmesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220302001554.1836066-1-matthew.d.roper@intel.com
parent adfadb56

drivers/gpu/drm/i915/gt/intel_engine.h

+2 −0
Original line number Diff line number Diff line
@@ -265,6 +265,8 @@ intel_engine_create_pinned_context(struct intel_engine_cs *engine, 


void intel_engine_destroy_pinned_context(struct intel_context *ce);



void xehp_enable_ccs_engines(struct intel_engine_cs *engine);



#define ENGINE_PHYSICAL	0

#define ENGINE_MOCK	1

#define ENGINE_VIRTUAL	2

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+17 −0
Original line number Diff line number Diff line
@@ -2070,6 +2070,23 @@ intel_engine_execlist_find_hung_request(struct intel_engine_cs *engine) 
	return active;

}



void xehp_enable_ccs_engines(struct intel_engine_cs *engine)

{

	/*

	 * If there are any non-fused-off CCS engines, we need to enable CCS

	 * support in the RCU_MODE register.  This only needs to be done once,

	 * so for simplicity we'll take care of this in the RCS engine's

	 * resume handler; since the RCS and all CCS engines belong to the

	 * same reset domain and are reset together, this will also take care

	 * of re-applying the setting after i915-triggered resets.

	 */

	if (!CCS_MASK(engine->gt))

		return;



	intel_uncore_write(engine->uncore, GEN12_RCU_MODE,

			   _MASKED_BIT_ENABLE(GEN12_RCU_MODE_CCS_ENABLE));

}



#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)

#include "mock_engine.c"

#include "selftest_engine.c"

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

+3 −0
Original line number Diff line number Diff line
@@ -2911,6 +2911,9 @@ static int execlists_resume(struct intel_engine_cs *engine) 


	enable_execlists(engine);



	if (engine->class == RENDER_CLASS)

		xehp_enable_ccs_engines(engine);



	return 0;

}

drivers/gpu/drm/i915/gt/intel_gt_regs.h

+3 −0
Original line number Diff line number Diff line
@@ -1327,6 +1327,9 @@ 
#define   ECOBITS_PPGTT_CACHE64B		(3 << 8)

#define   ECOBITS_PPGTT_CACHE4B			(0 << 8)



#define GEN12_RCU_MODE				_MMIO(0x14800)

#define   GEN12_RCU_MODE_CCS_ENABLE		REG_BIT(0)



#define CHV_FUSE_GT				_MMIO(VLV_DISPLAY_BASE + 0x2168)

#define   CHV_FGT_DISABLE_SS0			(1 << 10)

#define   CHV_FGT_DISABLE_SS1			(1 << 11)

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

+4 −0
Original line number Diff line number Diff line
@@ -335,6 +335,10 @@ static int guc_mmio_regset_init(struct temp_regset *regset, 
	ret |= GUC_MMIO_REG_ADD(regset, RING_HWS_PGA(base), false);

	ret |= GUC_MMIO_REG_ADD(regset, RING_IMR(base), false);



	if (engine->class == RENDER_CLASS &&

	    CCS_MASK(engine->gt))

		ret |= GUC_MMIO_REG_ADD(regset, GEN12_RCU_MODE, true);



	for (i = 0, wa = wal->list; i < wal->count; i++, wa++)

		ret |= GUC_MMIO_REG_ADD(regset, wa->reg, wa->masked_reg);