Commit 87793476 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86_cpu_for_v6.3_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpuid updates from Borislav Petkov:

 - Cache the AMD debug registers in per-CPU variables to avoid MSR
   writes where possible, when supporting a debug registers swap feature
   for SEV-ES guests

 - Add support for AMD's version of eIBRS called Automatic IBRS which is
   a set-and-forget control of indirect branch restriction speculation
   resources on privilege change

 - Add support for a new x86 instruction - LKGS - Load kernel GS which
   is part of the FRED infrastructure

 - Reset SPEC_CTRL upon init to accomodate use cases like kexec which
   rediscover

 - Other smaller fixes and cleanups

* tag 'x86_cpu_for_v6.3_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/amd: Cache debug register values in percpu variables
  KVM: x86: Propagate the AMD Automatic IBRS feature to the guest
  x86/cpu: Support AMD Automatic IBRS
  x86/cpu, kvm: Add the SMM_CTL MSR not present feature
  x86/cpu, kvm: Add the Null Selector Clears Base feature
  x86/cpu, kvm: Move X86_FEATURE_LFENCE_RDTSC to its native leaf
  x86/cpu, kvm: Add the NO_NESTED_DATA_BP feature
  KVM: x86: Move open-coded CPUID leaf 0x80000021 EAX bit propagation code
  x86/cpu, kvm: Add support for CPUID_80000021_EAX
  x86/gsseg: Add the new <asm/gsseg.h> header to <asm/asm-prototypes.h>
  x86/gsseg: Use the LKGS instruction if available for load_gs_index()
  x86/gsseg: Move load_gs_index() to its own new header file
  x86/gsseg: Make asm_load_gs_index() take an u16
  x86/opcode: Add the LKGS instruction to x86-opcode-map
  x86/cpufeature: Add the CPU feature bit for LKGS
  x86/bugs: Reset speculation control settings on init
  x86/cpu: Remove redundant extern x86_read_arch_cap_msr()
parents 74e19ef0 79146957

Documentation/admin-guide/hw-vuln/spectre.rst

+3 −3
Original line number Original line Diff line number Diff line
@@ -610,9 +610,9 @@ kernel command line. 
                retpoline,generic       Retpolines

                retpoline,generic       Retpolines

                retpoline,lfence        LFENCE; indirect branch

                retpoline,lfence        LFENCE; indirect branch

                retpoline,amd           alias for retpoline,lfence

                retpoline,amd           alias for retpoline,lfence

                eibrs                   enhanced IBRS

                eibrs                   Enhanced/Auto IBRS

                eibrs,retpoline         enhanced IBRS + Retpolines

                eibrs,retpoline         Enhanced/Auto IBRS + Retpolines

                eibrs,lfence            enhanced IBRS + LFENCE

                eibrs,lfence            Enhanced/Auto IBRS + LFENCE

                ibrs                    use IBRS to protect kernel

                ibrs                    use IBRS to protect kernel





		Not specifying this option is equivalent to

		Not specifying this option is equivalent to

Documentation/admin-guide/kernel-parameters.txt

+3 −3
Original line number Original line Diff line number Diff line
@@ -5740,9 +5740,9 @@ 
			retpoline,generic - Retpolines

			retpoline,generic - Retpolines

			retpoline,lfence  - LFENCE; indirect branch

			retpoline,lfence  - LFENCE; indirect branch

			retpoline,amd     - alias for retpoline,lfence

			retpoline,amd     - alias for retpoline,lfence

			eibrs		  - enhanced IBRS

			eibrs		  - Enhanced/Auto IBRS

			eibrs,retpoline   - enhanced IBRS + Retpolines

			eibrs,retpoline   - Enhanced/Auto IBRS + Retpolines

			eibrs,lfence      - enhanced IBRS + LFENCE

			eibrs,lfence      - Enhanced/Auto IBRS + LFENCE

			ibrs		  - use IBRS to protect kernel

			ibrs		  - use IBRS to protect kernel





			Not specifying this option is equivalent to

			Not specifying this option is equivalent to

arch/x86/entry/entry_64.S

+1 −1
Original line number Original line Diff line number Diff line
@@ -782,7 +782,7 @@ _ASM_NOKPROBE(common_interrupt_return) 




/*

/*

 * Reload gs selector with exception handling

 * Reload gs selector with exception handling

 * edi:  new selector

 *  di:  new selector

 *

 *

 * Is in entry.text as it shouldn't be instrumented.

 * Is in entry.text as it shouldn't be instrumented.

 */

 */

arch/x86/include/asm/asm-prototypes.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <asm/special_insns.h>

#include <asm/special_insns.h>

#include <asm/preempt.h>

#include <asm/preempt.h>

#include <asm/asm.h>

#include <asm/asm.h>

#include <asm/gsseg.h>





#ifndef CONFIG_X86_CMPXCHG64

#ifndef CONFIG_X86_CMPXCHG64

extern void cmpxchg8b_emu(void);

extern void cmpxchg8b_emu(void);

arch/x86/include/asm/cpufeature.h

+5 −2
Original line number Original line Diff line number Diff line
@@ -32,6 +32,7 @@ enum cpuid_leafs 
	CPUID_8000_0007_EBX,

	CPUID_8000_0007_EBX,

	CPUID_7_EDX,

	CPUID_7_EDX,

	CPUID_8000_001F_EAX,

	CPUID_8000_001F_EAX,

	CPUID_8000_0021_EAX,

};

};





#define X86_CAP_FMT_NUM "%d:%d"

#define X86_CAP_FMT_NUM "%d:%d"
@@ -94,8 +95,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 20, feature_bit) ||	\

	   REQUIRED_MASK_CHECK					  ||	\

	   REQUIRED_MASK_CHECK					  ||	\

	   BUILD_BUG_ON_ZERO(NCAPINTS != 20))

	   BUILD_BUG_ON_ZERO(NCAPINTS != 21))





#define DISABLED_MASK_BIT_SET(feature_bit)				\

#define DISABLED_MASK_BIT_SET(feature_bit)				\

	 ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  0, feature_bit) ||	\

	 ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK,  0, feature_bit) ||	\
@@ -118,8 +120,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; 
	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) ||	\

	   CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 20, feature_bit) ||	\

	   DISABLED_MASK_CHECK					  ||	\

	   DISABLED_MASK_CHECK					  ||	\

	   BUILD_BUG_ON_ZERO(NCAPINTS != 20))

	   BUILD_BUG_ON_ZERO(NCAPINTS != 21))





#define cpu_has(c, bit)							\

#define cpu_has(c, bit)							\

	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :	\

	(__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 :	\