Commit 87279fdf authored by Srinivasan Shanmugam's avatar Srinivasan Shanmugam Committed by Alex Deucher
Browse files

drm/amd/display: Clean up errors & warnings in amdgpu_dm.c 



Fix the following errors & warnings reported by checkpatch:

ERROR: space required before the open brace '{'
ERROR: space required before the open parenthesis '('
ERROR: that open brace { should be on the previous line
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: else should follow close brace '}'
ERROR: open brace '{' following function definitions go on the next line
ERROR: code indent should use tabs where possible

WARNING: braces {} are not necessary for single statement blocks
WARNING: void function return statements are not generally useful
WARNING: Block comments use * on subsequent lines
WARNING: Block comments use a trailing */ on a separate line

Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarSrinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b9c2213c

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+65 −68
Original line number Diff line number Diff line
@@ -1365,8 +1365,7 @@ static void dm_handle_hpd_rx_offload_work(struct work_struct *work) 
		DP_TEST_RESPONSE,

		&test_response.raw,

		sizeof(test_response));

	}

	else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&

	} else if ((dc_link->connector_signal != SIGNAL_TYPE_EDP) &&

			dc_link_check_link_loss_status(dc_link, &offload_work->data) &&

			dc_link_dp_allow_hpd_rx_irq(dc_link)) {

		/* offload_work->data is from handle_hpd_rx_irq->
@@ -1696,9 +1695,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) 
	if (amdgpu_dc_debug_mask & DC_DISABLE_STUTTER)

		adev->dm.dc->debug.disable_stutter = true;



	if (amdgpu_dc_debug_mask & DC_DISABLE_DSC) {

	if (amdgpu_dc_debug_mask & DC_DISABLE_DSC)

		adev->dm.dc->debug.disable_dsc = true;

	}



	if (amdgpu_dc_debug_mask & DC_DISABLE_CLOCK_GATING)

		adev->dm.dc->debug.disable_clock_gate = true;
@@ -1942,8 +1940,6 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) 
	mutex_destroy(&adev->dm.audio_lock);

	mutex_destroy(&adev->dm.dc_lock);

	mutex_destroy(&adev->dm.dpia_aux_lock);



	return;

}



static int load_dmcu_fw(struct amdgpu_device *adev)
@@ -2739,8 +2735,6 @@ static void dm_gpureset_commit_state(struct dc_state *dc_state, 


cleanup:

	kfree(bundle);



	return;

}



static int dm_resume(void *handle)
@@ -2954,8 +2948,7 @@ static const struct amd_ip_funcs amdgpu_dm_funcs = { 
	.set_powergating_state = dm_set_powergating_state,

};



const struct amdgpu_ip_block_version dm_ip_block =

{

const struct amdgpu_ip_block_version dm_ip_block = {

	.type = AMD_IP_BLOCK_TYPE_DCE,

	.major = 1,

	.minor = 0,
@@ -3000,9 +2993,12 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) 
	caps->ext_caps = &aconnector->dc_link->dpcd_sink_ext_caps;

	caps->aux_support = false;



	if (caps->ext_caps->bits.oled == 1 /*||

	    caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||

	    caps->ext_caps->bits.hdr_aux_backlight_control == 1*/)

	if (caps->ext_caps->bits.oled == 1

	    /*

	     * ||

	     * caps->ext_caps->bits.sdr_aux_backlight_control == 1 ||

	     * caps->ext_caps->bits.hdr_aux_backlight_control == 1

	     */)

		caps->aux_support = true;



	if (amdgpu_backlight == 0)
@@ -3269,6 +3265,7 @@ static void dm_handle_mst_sideband_msg(struct amdgpu_dm_connector *aconnector) 
		process_count < max_process_count) {

		u8 ack[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = {};

		u8 retry;



		dret = 0;



		process_count++;
@@ -3468,7 +3465,7 @@ static void register_hpd_handlers(struct amdgpu_device *adev) 
		aconnector = to_amdgpu_dm_connector(connector);

		dc_link = aconnector->dc_link;



		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {

		if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {

			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;

			int_params.irq_source = dc_link->irq_source_hpd;
@@ -3477,7 +3474,7 @@ static void register_hpd_handlers(struct amdgpu_device *adev) 
					(void *) aconnector);

		}



		if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {

		if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {



			/* Also register for DP short pulse (hpd_rx). */

			int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
@@ -3503,7 +3500,7 @@ static int dce60_register_irq_handlers(struct amdgpu_device *adev) 
	struct dc_interrupt_params int_params = {0};

	int r;

	int i;

	unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;

	unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;



	int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;

	int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
@@ -3517,7 +3514,8 @@ static int dce60_register_irq_handlers(struct amdgpu_device *adev) 
	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts

	 *    coming from DC hardware.

	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC

	 *    for acknowledging and handling. */

	 *    for acknowledging and handling.

	 */



	/* Use VBLANK interrupt */

	for (i = 0; i < adev->mode_info.num_crtc; i++) {
@@ -3585,7 +3583,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) 
	struct dc_interrupt_params int_params = {0};

	int r;

	int i;

	unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;

	unsigned int client_id = AMDGPU_IRQ_CLIENTID_LEGACY;



	if (adev->family >= AMDGPU_FAMILY_AI)

		client_id = SOC15_IH_CLIENTID_DCE;
@@ -3602,7 +3600,8 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) 
	 *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts

	 *    coming from DC hardware.

	 *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC

	 *    for acknowledging and handling. */

	 *    for acknowledging and handling.

	 */



	/* Use VBLANK interrupt */

	for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
@@ -4049,7 +4048,7 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, 
}



static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps,

				unsigned *min, unsigned *max)

				unsigned int *min, unsigned int *max)

{

	if (!caps)

		return 0;
@@ -4069,7 +4068,7 @@ static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, 
static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *caps,

					uint32_t brightness)

{

	unsigned min, max;

	unsigned int min, max;



	if (!get_brightness_range(caps, &min, &max))

		return brightness;
@@ -4082,7 +4081,7 @@ static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *c 
static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *caps,

				      uint32_t brightness)

{

	unsigned min, max;

	unsigned int min, max;



	if (!get_brightness_range(caps, &min, &max))

		return brightness;
@@ -4562,7 +4561,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) 
static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)

{

	drm_atomic_private_obj_fini(&dm->atomic_obj);

	return;

}



/******************************************************************************
@@ -5394,6 +5392,7 @@ static bool adjust_colour_depth_from_display_info( 
{

	enum dc_color_depth depth = timing_out->display_color_depth;

	int normalized_clk;



	do {

		normalized_clk = timing_out->pix_clk_100hz / 10;

		/* YCbCr 4:2:0 requires additional adjustment of 1/2 */
@@ -5609,6 +5608,7 @@ create_fake_sink(struct amdgpu_dm_connector *aconnector) 
{

	struct dc_sink_init_data sink_init_data = { 0 };

	struct dc_sink *sink = NULL;



	sink_init_data.link = aconnector->dc_link;

	sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
@@ -6028,7 +6028,7 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, 
		 * This may not be an error, the use case is when we have no

		 * usermode calls to reset and set mode upon hotplug. In this

		 * case, we call set mode ourselves to restore the previous mode

		 * and the modelist may not be filled in in time.

		 * and the modelist may not be filled in time.

		 */

		DRM_DEBUG_DRIVER("No preferred mode found\n");

	} else {
@@ -6817,6 +6817,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, 


	if (!state->duplicated) {

		int max_bpc = conn_state->max_requested_bpc;



		is_y420 = drm_mode_is_420_also(&connector->display_info, adjusted_mode) &&

			  aconnector->force_yuv420_output;

		color_depth = convert_color_depth_from_display_info(connector,
@@ -7454,7 +7455,6 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, 


	link->priv = aconnector;



	DRM_DEBUG_DRIVER("%s()\n", __func__);



	i2c = create_i2c(link->ddc, link->link_index, &res);

	if (!i2c) {
@@ -8176,8 +8176,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, 
			 * DRI3/Present extension with defined target_msc.

			 */

			last_flip_vblank = amdgpu_get_vblank_counter_kms(pcrtc);

		}

		else {

		} else {

			/* For variable refresh rate mode only:

			 * Get vblank of last completed flip to avoid > 1 vrr

			 * flips per video frame by use of throttling, but allow
@@ -8534,9 +8533,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) 
		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);



		drm_dbg_state(state->dev,

			"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "

			"planes_changed:%d, mode_changed:%d,active_changed:%d,"

			"connectors_changed:%d\n",

			"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",

			acrtc->crtc_id,

			new_crtc_state->enable,

			new_crtc_state->active,
@@ -9112,8 +9109,8 @@ static int do_aquire_global_lock(struct drm_device *dev, 
					&commit->flip_done, 10*HZ);



		if (ret == 0)

			DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done "

				  "timed out\n", crtc->base.id, crtc->name);

			DRM_ERROR("[CRTC:%d:%s] hw_done or flip_done timed out\n",

				  crtc->base.id, crtc->name);



		drm_crtc_commit_put(commit);

	}
@@ -9198,7 +9195,8 @@ is_timing_unchanged_for_freesync(struct drm_crtc_state *old_crtc_state, 
	return false;

}



static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state) {

static void set_freesync_fixed_config(struct dm_crtc_state *dm_new_crtc_state)

{

	u64 num, den, res;

	struct drm_crtc_state *new_crtc_state = &dm_new_crtc_state->base;
@@ -9320,9 +9318,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 
		goto skip_modeset;



	drm_dbg_state(state->dev,

		"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, "

		"planes_changed:%d, mode_changed:%d,active_changed:%d,"

		"connectors_changed:%d\n",

		"amdgpu_crtc id:%d crtc_state_flags: enable:%d, active:%d, planes_changed:%d, mode_changed:%d,active_changed:%d,connectors_changed:%d\n",

		acrtc->crtc_id,

		new_crtc_state->enable,

		new_crtc_state->active,
@@ -9351,8 +9347,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 
						     old_crtc_state)) {

			new_crtc_state->mode_changed = false;

			DRM_DEBUG_DRIVER(

				"Mode change not required for front porch change, "

				"setting mode_changed to %d",

				"Mode change not required for front porch change, setting mode_changed to %d",

				new_crtc_state->mode_changed);



			set_freesync_fixed_config(dm_new_crtc_state);
@@ -9364,10 +9359,9 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, 
			struct drm_display_mode *high_mode;



			high_mode = get_highest_refresh_rate_mode(aconnector, false);

			if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) {

			if (!drm_mode_equal(&new_crtc_state->mode, high_mode))

				set_freesync_fixed_config(dm_new_crtc_state);

		}

		}



		ret = dm_atomic_get_state(state, &dm_state);

		if (ret)
@@ -9534,6 +9528,7 @@ static bool should_reset_plane(struct drm_atomic_state *state, 
	 */

	for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {

		struct amdgpu_framebuffer *old_afb, *new_afb;



		if (other->type == DRM_PLANE_TYPE_CURSOR)

			continue;
@@ -9632,7 +9627,8 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc, 
	}



	/* Core DRM takes care of checking FB modifiers, so we only need to

	 * check tiling flags when the FB doesn't have a modifier. */

	 * check tiling flags when the FB doesn't have a modifier.

	 */

	if (!(fb->flags & DRM_MODE_FB_MODIFIERS)) {

		if (adev->family < AMDGPU_FAMILY_AI) {

			linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 &&
@@ -9858,12 +9854,12 @@ static int dm_check_crtc_cursor(struct drm_atomic_state *state, 
	/* On DCE and DCN there is no dedicated hardware cursor plane. We get a

	 * cursor per pipe but it's going to inherit the scaling and

	 * positioning from the underlying pipe. Check the cursor plane's

	 * blending properties match the underlying planes'. */

	 * blending properties match the underlying planes'.

	 */



	new_cursor_state = drm_atomic_get_new_plane_state(state, cursor);

	if (!new_cursor_state || !new_cursor_state->fb) {

	if (!new_cursor_state || !new_cursor_state->fb)

		return 0;

	}



	dm_get_oriented_plane_size(new_cursor_state, &cursor_src_w, &cursor_src_h);

	cursor_scale_w = new_cursor_state->crtc_w * 1000 / cursor_src_w;
@@ -9908,6 +9904,7 @@ static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm 
	struct drm_connector_state *conn_state, *old_conn_state;

	struct amdgpu_dm_connector *aconnector = NULL;

	int i;



	for_each_oldnew_connector_in_state(state, connector, old_conn_state, conn_state, i) {

		if (!conn_state->crtc)

			conn_state = old_conn_state;