Loading drivers/net/can/pch_can.c +1 −12 Original line number Diff line number Diff line Loading @@ -447,11 +447,6 @@ static void pch_can_release(struct pch_can_priv *priv) /* This function clears interrupt(s) from the CAN device. */ static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) { if (mask == PCH_STATUS_INT) { ioread32(&priv->regs->stat); return; } /* Clear interrupt for transmit object */ if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { /* Setting CMASK for clearing the reception interrupts. */ Loading Loading @@ -512,8 +507,6 @@ static void pch_can_error(struct net_device *ndev, u32 status) state = CAN_STATE_BUS_OFF; cf->can_id |= CAN_ERR_BUSOFF; can_bus_off(ndev); pch_can_set_run_mode(priv, PCH_CAN_RUN); dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__); } errc = ioread32(&priv->regs->errc); Loading Loading @@ -747,7 +740,7 @@ static int pch_can_poll(struct napi_struct *napi, int quota) if (!int_stat) goto end; if ((int_stat == PCH_STATUS_INT) && (quota > 0)) { if (int_stat == PCH_STATUS_INT) { reg_stat = ioread32(&priv->regs->stat); if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) { if (reg_stat & PCH_BUS_OFF || Loading Loading @@ -933,10 +926,6 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) priv->tx_obj++; } /* Reading the Msg Obj from the Msg RAM to the Interface register. */ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no); /* Setting the CMASK register. */ pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); Loading Loading
drivers/net/can/pch_can.c +1 −12 Original line number Diff line number Diff line Loading @@ -447,11 +447,6 @@ static void pch_can_release(struct pch_can_priv *priv) /* This function clears interrupt(s) from the CAN device. */ static void pch_can_int_clr(struct pch_can_priv *priv, u32 mask) { if (mask == PCH_STATUS_INT) { ioread32(&priv->regs->stat); return; } /* Clear interrupt for transmit object */ if ((mask >= PCH_RX_OBJ_START) && (mask <= PCH_RX_OBJ_END)) { /* Setting CMASK for clearing the reception interrupts. */ Loading Loading @@ -512,8 +507,6 @@ static void pch_can_error(struct net_device *ndev, u32 status) state = CAN_STATE_BUS_OFF; cf->can_id |= CAN_ERR_BUSOFF; can_bus_off(ndev); pch_can_set_run_mode(priv, PCH_CAN_RUN); dev_err(&ndev->dev, "%s -> Bus Off occurres.\n", __func__); } errc = ioread32(&priv->regs->errc); Loading Loading @@ -747,7 +740,7 @@ static int pch_can_poll(struct napi_struct *napi, int quota) if (!int_stat) goto end; if ((int_stat == PCH_STATUS_INT) && (quota > 0)) { if (int_stat == PCH_STATUS_INT) { reg_stat = ioread32(&priv->regs->stat); if (reg_stat & (PCH_BUS_OFF | PCH_LEC_ALL)) { if (reg_stat & PCH_BUS_OFF || Loading Loading @@ -933,10 +926,6 @@ static netdev_tx_t pch_xmit(struct sk_buff *skb, struct net_device *ndev) priv->tx_obj++; } /* Reading the Msg Obj from the Msg RAM to the Interface register. */ iowrite32(PCH_CMASK_RX_TX_GET, &priv->regs->ifregs[1].cmask); pch_can_rw_msg_obj(&priv->regs->ifregs[1].creq, tx_obj_no); /* Setting the CMASK register. */ pch_can_bit_set(&priv->regs->ifregs[1].cmask, PCH_CMASK_ALL); Loading