Commit 86e2eca4 authored by Grygorii Strashko's avatar Grygorii Strashko Committed by Paolo Abeni
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net: ethernet: ti: am65-cpsw: enable p0 host port rx_vlan_remap 



By default, the tagged ingress packets to the switch from the host port
P0 get internal switch priority assigned equal to the DMA CPPI channel
number they came from, unless CPSW_P0_CONTROL_REG.RX_REMAP_VLAN is enabled.
This causes issues with applying QoS policies and mapping packets on
external port fifos, because the default configuration is vlan_aware and
DMA CPPI channels are shared between all external ports.

Hence enable CPSW_P0_CONTROL_REG.RX_REMAP_VLAN so packet will preserve
internal switch priority assigned following the VLAN(priority) tag no
matter through which DMA CPPI Channels packets enter the switch.

Signed-off-by: default avatarGrygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: default avatarSiddharth Vadapalli <s-vadapalli@ti.com>
Link: https://lore.kernel.org/r/20230327092103.3256118-1-s-vadapalli@ti.com


Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent 5c8560c4

drivers/net/ethernet/ti/am65-cpsw-nuss.c

+3 −2
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ 


/* AM65_CPSW_P0_REG_CTL */

#define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN	BIT(0)

#define AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN	BIT(16)



/* AM65_CPSW_PORT_REG_PRI_CTL */

#define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN	BIT(8)
@@ -385,8 +386,8 @@ static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 
	/* set base flow_id */

	writel(common->rx_flow_id_base,

	       host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET);

	/* en tx crc offload */

	writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL);

	writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN,

	       host_p->port_base + AM65_CPSW_P0_REG_CTL);



	am65_cpsw_nuss_set_p0_ptype(common);