Commit 86df4141 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Introduce G12 subplatform of DG2



Another fork of the DG2 design has appeared, known as "DG2-G12;" let's
add it as a new subplatform.  As with G11, the GT stepping resets back
to A0 (so a DG2-G12 A0 is similar, but not identical, to a DG2-G10 C0)
but the display steppings continue to use the same numbering scheme as
G10 and G11.

Some existing DG2 workarounds are starting to be extended to the DG2-G12
subplatform.  So far only workarounds that were "permanent" for both
DG2-G10 and DG2-G11 have been tagged for DG2-G12, but more
stepping-specific workarounds are likely to show up in the future.

Bspec: 44477
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarRadhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220120235016.1209326-1-matthew.d.roper@intel.com
parent 29b9702f
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+1 −1
Original line number Diff line number Diff line
@@ -2087,7 +2087,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
	}

	if (IS_DG2_GRAPHICS_STEP(i915, G10, STEP_B0, STEP_FOREVER) ||
	    IS_DG2_G11(i915)) {
	    IS_DG2_G11(i915) || IS_DG2_G12(i915)) {
		/* Wa_22013037850:dg2 */
		wa_write_or(wal, LSC_CHICKEN_BIT_0_UDW,
			    DISABLE_128B_EVICTION_COMMAND_UDW);
+11 −8
Original line number Diff line number Diff line
@@ -1284,6 +1284,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
#define IS_DG2_G11(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
#define IS_DG2_G12(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G12)
#define IS_ADLS_RPLS(dev_priv) \
	IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S)
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
@@ -1398,16 +1400,17 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
	(IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))

/*
 * DG2 hardware steppings are a bit unusual.  The hardware design was forked
 * to create two variants (G10 and G11) which have distinct workaround sets.
 * The G11 fork of the DG2 design resets the GT stepping back to "A0" for its
 * first iteration, even though it's more similar to a G10 B0 stepping in terms
 * of functionality and workarounds.  However the display stepping does not
 * reset in the same manner --- a specific stepping like "B0" has a consistent
 * meaning regardless of whether it belongs to a G10 or G11 DG2.
 * DG2 hardware steppings are a bit unusual.  The hardware design was forked to
 * create three variants (G10, G11, and G12) which each have distinct
 * workaround sets.  The G11 and G12 forks of the DG2 design reset the GT
 * stepping back to "A0" for their first iterations, even though they're more
 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
 * functionality and workarounds.  However the display stepping does not reset
 * in the same manner --- a specific stepping like "B0" has a consistent
 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
 *
 * TLDR:  All GT workarounds and stepping-specific logic must be applied in
 * relation to a specific subplatform (G10 or G11), whereas display workarounds
 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
 * and stepping-specific logic will be applied with a general DG2-wide stepping
 * number.
 */
+2 −1
Original line number Diff line number Diff line
@@ -96,7 +96,7 @@ enum intel_platform {
 * it is fine for the same bit to be used on multiple parent platforms.
 */

#define INTEL_SUBPLATFORM_BITS (2)
#define INTEL_SUBPLATFORM_BITS (3)
#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)

/* HSW/BDW/SKL/KBL/CFL */
@@ -109,6 +109,7 @@ enum intel_platform {
/* DG2 */
#define INTEL_SUBPLATFORM_G10	0
#define INTEL_SUBPLATFORM_G11	1
#define INTEL_SUBPLATFORM_G12	2

/* ADL-S */
#define INTEL_SUBPLATFORM_RPL_S	0
+7 −0
Original line number Diff line number Diff line
@@ -122,6 +122,10 @@ static const struct intel_step_info dg2_g11_revid_step_tbl[] = {
	[0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 },
};

static const struct intel_step_info dg2_g12_revid_step_tbl[] = {
	[0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_C0 },
};

static const struct intel_step_info adls_rpls_revids[] = {
	[0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 },
	[0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 },
@@ -140,6 +144,9 @@ void intel_step_init(struct drm_i915_private *i915)
	} else if (IS_DG2_G11(i915)) {
		revids = dg2_g11_revid_step_tbl;
		size = ARRAY_SIZE(dg2_g11_revid_step_tbl);
	} else if (IS_DG2_G12(i915)) {
		revids = dg2_g12_revid_step_tbl;
		size = ARRAY_SIZE(dg2_g12_revid_step_tbl);
	} else if (IS_XEHPSDV(i915)) {
		revids = xehpsdv_revids;
		size = ARRAY_SIZE(xehpsdv_revids);