Commit 86c87bea authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull devicetree updates from Rob Herring:
 "Bindings:

   - Convert smsc,lan91c111, qcom,spi-qup, qcom,msm-uartdm,
     qcom,i2c-qup, qcom,gsbi, i2c-mt65xx, TI wkup_m3_ipc (and new
     props), qcom,smp2p, TI timer, Mediatek gnss, Mediatek topckgen,
     Mediatek apmixedsys, Mediatek infracfg, fsl,ls-extirq,
     fsl,layerscape-dcfg, QCom PMIC SPMI, rda,8810pl-timer, Xilinx
     zynqmp_ipi, uniphier-pcie, and Ilitek touchscreen controllers

   - Convert various Arm Ltd peripheral IP bindings to schemas

   - New bindings for Menlo board CPLD, DH electronics board CPLD,
     Qualcomm Geni based QUP I2C, Renesas RZ/G2UL OSTM, Broafcom BCM4751
     GNSS, MT6360 PMIC, ASIX USB Ethernet controllers, and
     Microchip/SMSC LAN95xx USB Ethernet controllers

   - Add vendor prefix for Enclustra

   - Add various compatible string additions

   - Various example fixes and cleanups

   - Remove unused hisilicon,hi6220-reset binding

   - Treewide fix properties missing type definition

   - Drop some empty and unreferenced .txt bindings

   - Documentation improvements for writing schemas

  DT driver core:

   - Drop static IRQ resources for DT platform devices as IRQ setup is
     dynamic and drivers have all been converted to use
     platform_get_irq() and friends

   - Rework memory allocations and frees for overlays

   - Continue overlay notifier callbacks on successful calls and add
     unittests

   - Handle 'interrupts-extended' in early DT IRQ setup

   - Fix of_property_read_string() errors to match documentation

   - Ignore disabled nodes in FDT API calls"

* tag 'devicetree-for-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (86 commits)
  of/irq: fix typo in comment
  dt-bindings: Fix properties without any type
  Revert "dt-bindings: mailbox: qcom-ipcc: add missing properties into example"
  dt-bindings: input: touchscreen: ilitek_ts_i2c: Absorb ili2xxx bindings
  dt-bindings: timer: samsung,exynos4210-mct: define strict clock order
  dt-bindings: timer: samsung,exynos4210-mct: drop unneeded minItems
  dt-bindings: timer: cdns,ttc: drop unneeded minItems
  dt-bindings: mailbox: zynqmp_ipi: convert to yaml
  dt-bindings: usb: ci-hdrc-usb2: fix node node for ethernet controller
  dt-bindings: net: add schema for Microchip/SMSC LAN95xx USB Ethernet controllers
  dt-bindings: net: add schema for ASIX USB Ethernet controllers
  of/fdt: Ignore disabled memory nodes
  dt-bindings: arm: fix typos in compatible
  dt-bindings: mfd: Add bindings child nodes for the Mediatek MT6360
  dt-bindings: display: convert Arm Komeda to DT schema
  dt-bindings: display: convert Arm Mali-DP to DT schema
  dt-bindings: display: convert Arm HDLCD to DT schema
  dt-bindings: display: convert PL110/PL111 to DT schema
  dt-bindings: arm: convert vexpress-config to DT schema
  dt-bindings: arm: convert vexpress-sysregs to DT schema
  ...
parents d223575e d036d915
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@@ -30,7 +30,7 @@ Example:

	cpus {
		cpu@0 {
			compatible = "arm,cotex-a9";
			compatible = "arm,cortex-a9";
			reg = <0>;
			...
			enable-method = "brcm,bcm63138";
+0 −19
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Freescale DCFG

DCFG is the device configuration unit, that provides general purpose
configuration and status for the device. Such as setting the secondary
core start address and release the secondary core from holdoff and startup.

Required properties:
  - compatible: Should contain a chip-specific compatible string,
	Chip-specific strings are of the form "fsl,<chip>-dcfg",
	The following <chip>s are known to be supported:
	ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a

  - reg : should contain base address and length of DCFG memory-mapped registers

Example:
	dcfg: dcfg@1ee0000 {
		compatible = "fsl,ls1021a-dcfg";
		reg = <0x0 0x1ee0000 0x0 0x10000>;
	};
+0 −19
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Freescale SCFG

SCFG is the supplemental configuration unit, that provides SoC specific
configuration and status registers for the chip. Such as getting PEX port
status.

Required properties:
  - compatible: Should contain a chip-specific compatible string,
	Chip-specific strings are of the form "fsl,<chip>-scfg",
	The following <chip>s are known to be supported:
	ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.

  - reg: should contain base address and length of SCFG memory-mapped registers

Example:
	scfg: scfg@1570000 {
		compatible = "fsl,ls1021a-scfg";
		reg = <0x0 0x1570000 0x0 0x10000>;
	};
+3 −2
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@@ -17,14 +17,15 @@ properties:
      - const: hisilicon,hip04-bootwrapper

  boot-method:
    $ref: /schemas/types.yaml#/definitions/uint32-array
    description: |
      Address and size of boot method.
      [0]: bootwrapper physical address
      [1]: bootwrapper size
      [2]: relocation physical address
      [3]: relocation size
    minItems: 1
    maxItems: 2
    minItems: 2
    maxItems: 4

required:
  - compatible
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Mediatek apmixedsys controller
==============================

The Mediatek apmixedsys controller provides the PLLs to the system.

Required Properties:

- compatible: Should be one of:
	- "mediatek,mt2701-apmixedsys"
	- "mediatek,mt2712-apmixedsys", "syscon"
	- "mediatek,mt6765-apmixedsys", "syscon"
	- "mediatek,mt6779-apmixedsys", "syscon"
	- "mediatek,mt6797-apmixedsys"
	- "mediatek,mt7622-apmixedsys"
	- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
	- "mediatek,mt7629-apmixedsys"
	- "mediatek,mt7986-apmixedsys"
	- "mediatek,mt8135-apmixedsys"
	- "mediatek,mt8167-apmixedsys", "syscon"
	- "mediatek,mt8173-apmixedsys"
	- "mediatek,mt8183-apmixedsys", "syscon"
	- "mediatek,mt8516-apmixedsys"
- #clock-cells: Must be 1

The apmixedsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.

Example:

apmixedsys: clock-controller@10209000 {
	compatible = "mediatek,mt8173-apmixedsys";
	reg = <0 0x10209000 0 0x1000>;
	#clock-cells = <1>;
};
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