Commit 86c457e3 authored by Chuanhua Han's avatar Chuanhua Han Committed by Shawn Guo
Browse files

arm64: dts: ls1088a: Fix incorrect I2C clock divider 



Ls1088a platform, the i2c input clock is actually platform pll CLK / 8
(this is the hardware connection), other clock divider can not get the
correct i2c clock, resulting in the output of SCL pin clock is not
accurate.

Signed-off-by: default avatarChuanhua Han <chuanhua.han@nxp.com>
Acked-by: default avatarLi Yang <leoyang.li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent f64697bd

arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -328,7 +328,7 @@ 
			#size-cells = <0>;

			reg = <0x0 0x2000000 0x0 0x10000>;

			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen 4 7>;

			status = "disabled";

		};
@@ -338,7 +338,7 @@ 
			#size-cells = <0>;

			reg = <0x0 0x2010000 0x0 0x10000>;

			interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen 4 7>;

			status = "disabled";

		};
@@ -348,7 +348,7 @@ 
			#size-cells = <0>;

			reg = <0x0 0x2020000 0x0 0x10000>;

			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen 4 7>;

			status = "disabled";

		};
@@ -358,7 +358,7 @@ 
			#size-cells = <0>;

			reg = <0x0 0x2030000 0x0 0x10000>;

			interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&clockgen 4 3>;

			clocks = <&clockgen 4 7>;

			status = "disabled";

		};