Commit 86c0ef72 authored by Anusha Srivatsa's avatar Anusha Srivatsa
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drm/i915/display: Add CDCLK Support for MTL 



As per bSpec MTL has 38.4 MHz Reference clock.
Adding the cdclk tables and cdclk_funcs that MTL
will use.

v2: Revert to using bxt_get_cdclk()

BSpec: 65243

Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: default avatarAnusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: default avatarClint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221117230002.792096-3-anusha.srivatsa@intel.com
parent 25e0e5ae

drivers/gpu/drm/i915/display/intel_cdclk.c

+21 −1
Original line number Diff line number Diff line
@@ -1346,6 +1346,16 @@ static const struct intel_cdclk_vals dg2_cdclk_table[] = { 
	{}

};



static const struct intel_cdclk_vals mtl_cdclk_table[] = {

	{ .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },

	{ .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },

	{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },

	{ .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },

	{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },

	{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },

	{}

};



static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)

{

	const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3190,6 +3200,13 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) 
	return freq;

}



static const struct intel_cdclk_funcs mtl_cdclk_funcs = {

	.get_cdclk = bxt_get_cdclk,

	.set_cdclk = bxt_set_cdclk,

	.modeset_calc_cdclk = bxt_modeset_calc_cdclk,

	.calc_voltage_level = tgl_calc_voltage_level,

};



static const struct intel_cdclk_funcs tgl_cdclk_funcs = {

	.get_cdclk = bxt_get_cdclk,

	.set_cdclk = bxt_set_cdclk,
@@ -3325,7 +3342,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = { 
 */

void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)

{

	if (IS_DG2(dev_priv)) {

	if (IS_METEORLAKE(dev_priv)) {

		dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;

		dev_priv->display.cdclk.table = mtl_cdclk_table;

	} else if (IS_DG2(dev_priv)) {

		dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;

		dev_priv->display.cdclk.table = dg2_cdclk_table;

	} else if (IS_ALDERLAKE_P(dev_priv)) {