PCI: Fix typos in docs and comments (86b4ad7d) · Commits · EulixOS / Software / Kernel

Documentation/PCI/pci-error-recovery.rst

+6 −6

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		@@ -17,7 +17,7 @@ chipsets are able to deal with these errors; these include PCI-E chipsets,
		and the PCI-host bridges found on IBM Power4, Power5 and Power6-based
		pSeries boxes. A typical action taken is to disconnect the affected device,
		halting all I/O to it. The goal of a disconnection is to avoid system
		corruption; for example, to halt system memory corruption due to DMA's
		corruption; for example, to halt system memory corruption due to DMAs
		to "wild" addresses. Typically, a reconnection mechanism is also
		offered, so that the affected PCI device(s) are reset and put back
		into working condition. The reset phase requires coordination
		@@ -178,9 +178,9 @@ is STEP 6 (Permanent Failure).
		complex and not worth implementing.

		The current powerpc implementation doesn't much care if the device
		attempts I/O at this point, or not. I/O's will fail, returning
		attempts I/O at this point, or not. I/Os will fail, returning
		a value of 0xff on read, and writes will be dropped. If more than
		EEH_MAX_FAILS I/O's are attempted to a frozen adapter, EEH
		EEH_MAX_FAILS I/Os are attempted to a frozen adapter, EEH
		assumes that the device driver has gone into an infinite loop
		and prints an error to syslog. A reboot is then required to
		get the device working again.
		@@ -204,7 +204,7 @@ instead will have gone directly to STEP 3 (Link Reset) or STEP 4 (Slot Reset)
		.. note::

		The following is proposed; no platform implements this yet:
		Proposal: All I/O's should be done _synchronously_ from within
		Proposal: All I/Os should be done _synchronously_ from within
		this callback, errors triggered by them will be returned via
		the normal pci_check_whatever() API, no new error_detected()
		callback will be issued due to an error happening here. However,
		@@ -258,7 +258,7 @@ Powerpc platforms implement two levels of slot reset:
		soft reset(default) and fundamental(optional) reset.

		Powerpc soft reset consists of asserting the adapter #RST line and then
		restoring the PCI BAR's and PCI configuration header to a state
		restoring the PCI BARs and PCI configuration header to a state
		that is equivalent to what it would be after a fresh system
		power-on followed by power-on BIOS/system firmware initialization.
		Soft reset is also known as hot-reset.
		@@ -362,7 +362,7 @@ permanent failure in some way. If the device is hotplug-capable,
		the operator will probably want to remove and replace the device.
		Note, however, not all failures are truly "permanent". Some are
		caused by over-heating, some by a poorly seated card. Many
		PCI error events are caused by software bugs, e.g. DMA's to
		PCI error events are caused by software bugs, e.g. DMAs to
		wild addresses or bogus split transactions due to programming
		errors. See the discussion in Documentation/powerpc/eeh-pci-error-recovery.rst
		for additional detail on real-life experience of the causes of

drivers/pci/controller/cadence/pcie-cadence.h

+1 −1

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		@@ -32,7 +32,7 @@
		#define CDNS_PCIE_LM_ID_SUBSYS(sub) \
		(((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)

		/* Root Port Requestor ID Register */
		/* Root Port Requester ID Register */
		#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
		#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
		#define CDNS_PCIE_LM_RP_RID_SHIFT 0

drivers/pci/endpoint/functions/pci-epf-vntb.c

+16 −16

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		@@ -988,20 +988,20 @@ static struct config_group epf_ntb_add_cfs(struct pci_epf epf,
		static u32 pci_space[] = {
		0xffffffff, /* Device ID, Vendor ID */
		0, /* Status, Command */
		0xffffffff, /Class code, subclass, prog if, revision id/
		0x40, /bist, header type, latency Timer, cache line size/
		0xffffffff, /* Base Class, Subclass, Prog Intf, Revision ID */
		0x40, /* BIST, Header Type, Latency Timer, Cache Line Size */
		0, /* BAR 0 */
		0, /* BAR 1 */
		0, /* BAR 2 */
		0, /* BAR 3 */
		0, /* BAR 4 */
		0, /* BAR 5 */
		0, /Cardbus cis point/
		0, /Subsystem ID Subystem vendor id/
		0, /* Cardbus CIS Pointer */
		0, /* Subsystem ID, Subsystem Vendor ID */
		0, /* ROM Base Address */
		0, /Reserved, Cap. Point/
		0, /Reserved,/
		0, /Max Lat, Min Gnt, interrupt pin, interrupt line/
		0, /* Reserved, Capabilities Pointer */
		0, /* Reserved */
		0, /* Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line */
		};

		static int pci_read(struct pci_bus bus, unsigned int devfn, int where, int size, u32 val)

drivers/pci/msi/irqdomain.c

+2 −2

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		@@ -336,7 +336,7 @@ bool pci_msi_domain_supports(struct pci_dev *pdev, unsigned int feature_mask,
		if (!irq_domain_is_msi_parent(domain)) {
		/*
		* For "global" PCI/MSI interrupt domains the associated
		* msi_domain_info::flags is the authoritive source of
		* msi_domain_info::flags is the authoritative source of
		* information.
		*/
		info = domain->host_data;
		@@ -344,7 +344,7 @@ bool pci_msi_domain_supports(struct pci_dev *pdev, unsigned int feature_mask,
		} else {
		/*
		* For MSI parent domains the supported feature set
		* is avaliable in the parent ops. This makes checks
		* is available in the parent ops. This makes checks
		* possible before actually instantiating the
		* per device domain because the parent is never
		* expanding the PCI/MSI functionality.

drivers/pci/p2pdma.c

+1 −1

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		@@ -435,7 +435,7 @@ static const struct pci_p2pdma_whitelist_entry {
		/* Intel Xeon E7 v3/Xeon E5 v3/Core i7 */
		{PCI_VENDOR_ID_INTEL, 0x2f00, REQ_SAME_HOST_BRIDGE},
		{PCI_VENDOR_ID_INTEL, 0x2f01, REQ_SAME_HOST_BRIDGE},
		/* Intel SkyLake-E */
		/* Intel Skylake-E */
		{PCI_VENDOR_ID_INTEL, 0x2030, 0},
		{PCI_VENDOR_ID_INTEL, 0x2031, 0},
		{PCI_VENDOR_ID_INTEL, 0x2032, 0},