Unverified Commit 86a8557e authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!3113 KVM: arm64: limit PMU version to PMUv3 for ARMv8.1 

Merge Pull Request from: @zhang-yuans 
 
PR sync from: Zhang Yuan zhangyuan162@huawei.com
https://lore.kernel.org/stable/20231128074633.646-1-yuzenghui@huawei.com/

bugzilla: https://gitee.com/src-openeuler/kernel/issues/I8K8XV
 
 
Link:https://gitee.com/openeuler/kernel/pulls/3113

 

Reviewed-by: default avatarZenghui Yu <yuzenghui@huawei.com>
Reviewed-by: default avatarXiongfeng Wang <wangxiongfeng2@huawei.com>
Signed-off-by: default avatarZhang Changzhong <zhangchangzhong@huawei.com>
parents 2025d2bd fe19b95e

arch/arm64/include/asm/cpufeature.h

+23 −0
Original line number Diff line number Diff line
@@ -447,6 +447,29 @@ cpuid_feature_extract_unsigned_field(u64 features, int field) 
	return cpuid_feature_extract_unsigned_field_width(features, field, 4);

}



/*

 * Fields that identify the version of the Performance Monitors Extension do

 * not follow the standard ID scheme. See ARM DDI 0487E.a page D13-2825,

 * "Alternative ID scheme used for the Performance Monitors Extension version".

 */

static inline u64 __attribute_const__

cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap)

{

       u64 val = cpuid_feature_extract_unsigned_field(features, field);

       u64 mask = GENMASK_ULL(field + 3, field);



       /* Treat IMPLEMENTATION DEFINED functionality as unimplemented */

       if (val == 0xf)

               val = 0;



       if (val > cap) {

               features &= ~mask;

               features |= (cap << field) & mask;

       }



       return features;

}



static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)

{

	return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);

arch/arm64/include/asm/sysreg.h

+6 −0
Original line number Diff line number Diff line
@@ -619,6 +619,12 @@ 
#define ID_AA64DFR0_TRACEVER_SHIFT	4

#define ID_AA64DFR0_DEBUGVER_SHIFT	0



#define ID_AA64DFR0_PMUVER_8_1          0x4



#define ID_DFR0_PERFMON_SHIFT           24



#define ID_DFR0_PERFMON_8_1             0x4



#define ID_ISAR5_RDM_SHIFT		24

#define ID_ISAR5_CRC32_SHIFT		16

#define ID_ISAR5_SHA2_SHIFT		12

arch/arm64/kvm/sys_regs.c

+10 −0
Original line number Diff line number Diff line
@@ -1082,6 +1082,16 @@ static u64 read_id_reg(struct kvm_vcpu *vcpu, 
			kvm_debug("LORegions unsupported for guests, suppressing\n");



		val &= ~(0xfUL << ID_AA64MMFR1_LOR_SHIFT);

	} else if (id == SYS_ID_AA64DFR0_EL1) {

		/* Limit guests to PMUv3 for ARMv8.1 */

		val = cpuid_feature_cap_perfmon_field(val,

						ID_AA64DFR0_PMUVER_SHIFT,

						ID_AA64DFR0_PMUVER_8_1);

	} else if (id == SYS_ID_DFR0_EL1) {

		/* Limit guests to PMUv3 for ARMv8.1 */

		val = cpuid_feature_cap_perfmon_field(val,

						ID_DFR0_PERFMON_SHIFT,

						ID_DFR0_PERFMON_8_1);

	}



	return val;