Commit 869f0ec0 authored by Rob Herring's avatar Rob Herring Committed by Shawn Guo
Browse files

arm64: dts: freescale: Fix 'interrupt-map' parent address cells 



The 'interrupt-map' in several Layerscape SoCs is malformed. The
'#address-cells' size of the parent interrupt controller (the GIC) is not
accounted for.

Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Li Yang <leoyang.li@nxp.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarLi Yang <leoyang.li@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent caa355c5

arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

+12 −12
Original line number Diff line number Diff line
@@ -241,18 +241,18 @@ 
				interrupt-controller;

				reg = <0x14 4>;

				interrupt-map =

					<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

					<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

					<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

					<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

					<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

					<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

					<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

					<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

					<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

					<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

					<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

					<0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

					<1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

					<2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

					<3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

					<4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

					<5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

					<6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

					<7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

					<8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					<9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

					<10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

					<11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-map-mask = <0xffffffff 0x0>;

			};

		};

arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi

+12 −12
Original line number Diff line number Diff line
@@ -293,18 +293,18 @@ 
				interrupt-controller;

				reg = <0x14 4>;

				interrupt-map =

					<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

					<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

					<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

					<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

					<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

					<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

					<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

					<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

					<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

					<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

					<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

					<0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

					<1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

					<2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

					<3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

					<4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

					<5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

					<6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

					<7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

					<8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					<9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

					<10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

					<11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-map-mask = <0xffffffff 0x0>;

			};

		};

arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi

+12 −12
Original line number Diff line number Diff line
@@ -680,18 +680,18 @@ 
				interrupt-controller;

				reg = <0x14 4>;

				interrupt-map =

					<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

					<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

					<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

					<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

					<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

					<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

					<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

					<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

					<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

					<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

					<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

					<0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,

					<1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,

					<2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,

					<3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,

					<4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,

					<5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,

					<6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,

					<7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,

					<8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

					<9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,

					<10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,

					<11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;

				interrupt-map-mask = <0xffffffff 0x0>;

			};

		};