Commit 869decd1 authored by Tero Kristo's avatar Tero Kristo Committed by Stephen Boyd
Browse files

clk: ti: dra7: disable the RNG and TIMER12 clkctrl clocks on HS devices 



RNG and TIMER12 are reserved for secure side usage only on HS devices,
so disable their clkctrl clocks on HS SoCs also.

Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
Tested-by: default avatarAndrew F. Davis <afd@ti.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 2b1202d7

arch/arm/mach-omap2/clock.c

+3 −0
Original line number Diff line number Diff line
@@ -119,6 +119,9 @@ void __init ti_clk_init_features(void) 
	if (cpu_is_omap343x())

		features.flags |= TI_CLK_DPLL_HAS_FREQSEL;



	if (omap_type() == OMAP2_DEVICE_TYPE_GP)

		features.flags |= TI_CLK_DEVICE_TYPE_GP;



	/* Idlest value for interface clocks.

	 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.

	 * 34xx reverses this, just to keep us on our toes

drivers/clk/ti/clk-7xx-compat.c

+2 −2
Original line number Diff line number Diff line
@@ -662,7 +662,7 @@ static const struct omap_clkctrl_reg_data dra7_l4per_clkctrl_regs[] __initconst 
	{ DRA7_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },

	{ DRA7_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },

	{ DRA7_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },

	{ DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },

	{ DRA7_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "l3_iclk_div", "l4sec_clkdm" },

	{ DRA7_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div", "l4sec_clkdm" },

	{ DRA7_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01d0:24", "l4per2_clkdm" },

	{ DRA7_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per_cm:clk:01e0:24", "l4per2_clkdm" },
@@ -704,7 +704,7 @@ static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initcons 
	{ DRA7_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },

	{ DRA7_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },

	{ DRA7_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0020:24" },

	{ DRA7_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },

	{ DRA7_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },

	{ DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },

	{ DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },

	{ DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },

drivers/clk/ti/clk-7xx.c

+2 −2
Original line number Diff line number Diff line
@@ -590,7 +590,7 @@ static const struct omap_clkctrl_reg_data dra7_l4sec_clkctrl_regs[] __initconst 
	{ DRA7_L4SEC_AES1_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },

	{ DRA7_L4SEC_AES2_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },

	{ DRA7_L4SEC_DES_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },

	{ DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP, "" },

	{ DRA7_L4SEC_RNG_CLKCTRL, NULL, CLKF_HW_SUP | CLKF_SOC_NONSEC, "" },

	{ DRA7_L4SEC_SHAM_CLKCTRL, NULL, CLKF_HW_SUP, "l3_iclk_div" },

	{ 0 },

};
@@ -757,7 +757,7 @@ static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initcons 
	{ DRA7_WKUPAON_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },

	{ DRA7_WKUPAON_GPIO1_CLKCTRL, dra7_gpio1_bit_data, CLKF_HW_SUP, "wkupaon_iclk_mux" },

	{ DRA7_WKUPAON_TIMER1_CLKCTRL, dra7_timer1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0020:24" },

	{ DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, 0, "secure_32k_clk_src_ck" },

	{ DRA7_WKUPAON_TIMER12_CLKCTRL, NULL, CLKF_SOC_NONSEC, "secure_32k_clk_src_ck" },

	{ DRA7_WKUPAON_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },

	{ DRA7_WKUPAON_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0060:24" },

	{ DRA7_WKUPAON_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon-clkctrl:0068:24" },

drivers/clk/ti/clkctrl.c

+3 −0
Original line number Diff line number Diff line
@@ -509,6 +509,9 @@ static void __init _ti_omap4_clkctrl_setup(struct device_node *node) 
		data = dm816_clkctrl_data;

#endif



	if (ti_clk_get_features()->flags & TI_CLK_DEVICE_TYPE_GP)

		soc_mask |= CLKF_SOC_NONSEC;



	while (data->addr) {

		if (addr == data->addr)

			break;

drivers/clk/ti/clock.h

+5 −4
Original line number Diff line number Diff line
@@ -83,11 +83,12 @@ enum { 
#define CLKF_HW_SUP			BIT(6)

#define CLKF_NO_IDLEST			BIT(7)



#define CLKF_SOC_MASK			GENMASK(10, 8)

#define CLKF_SOC_MASK			GENMASK(11, 8)



#define CLKF_SOC_DRA72			BIT(8)

#define CLKF_SOC_DRA74			BIT(9)

#define CLKF_SOC_DRA76			BIT(10)

#define CLKF_SOC_NONSEC			BIT(8)

#define CLKF_SOC_DRA72			BIT(9)

#define CLKF_SOC_DRA74			BIT(10)

#define CLKF_SOC_DRA76			BIT(11)



#define CLK(dev, con, ck)		\

	{				\