Commit 868b70b9 authored by Paul Cercueil's avatar Paul Cercueil Committed by Thomas Bogendoerfer
Browse files

MIPS: DTS: CI20: Parent MSCMUX clock to MPLL 



This makes it possible to clock the SD cards much higher, as the MPLL is
running at 1.2 GHz by default. The previous parent was the EXT clock,
which caused the SD cards to be clocked at 24 MHz maximum.

Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 5fe60d3b

arch/mips/boot/dts/ingenic/ci20.dts

+3 −2
Original line number Diff line number Diff line
@@ -129,10 +129,11 @@ 
	 */

	assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,

			  <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>,

			  <&cgu JZ4780_CLK_HDMI>;

			  <&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_MSCMUX>;

	assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,

				 <&cgu JZ4780_CLK_MPLL>,

				 <&cgu JZ4780_CLK_SSIPLL>;

				 <&cgu JZ4780_CLK_SSIPLL>,

				 <0>, <&cgu JZ4780_CLK_MPLL>;

	assigned-clock-rates = <48000000>, <0>, <54000000>, <0>, <27000000>;

};