Unverified Commit 8658db0a authored by Heiko Stuebner's avatar Heiko Stuebner Committed by Palmer Dabbelt
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RISC-V: move some stray __RISCV_INSN_FUNCS definitions from kprobes 



The __RISCV_INSN_FUNCS originally declared riscv_insn_is_* functions inside
the kprobes implementation. This got moved into a central header in
commit ec5f9087 ("RISC-V: Move riscv_insn_is_* macros into a common header").

Though it looks like I overlooked two of them, so fix that. FENCE itself is
an instruction defined directly by its own opcode, while the created
riscv_isn_is_system function covers all instructions defined under the SYSTEM
opcode.

Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Signed-off-by: default avatarHeiko Stuebner <heiko.stuebner@vrull.eu>
Link: https://lore.kernel.org/r/20230113211955.3534431-1-heiko@sntech.de


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent ec631191

arch/riscv/include/asm/insn.h

+10 −0
Original line number Diff line number Diff line
@@ -128,6 +128,7 @@ 
#define RVC_C2_RD_OPOFF		7



/* parts of opcode for RVG*/

#define RVG_OPCODE_FENCE	0x0f

#define RVG_OPCODE_AUIPC	0x17

#define RVG_OPCODE_BRANCH	0x63

#define RVG_OPCODE_JALR		0x67
@@ -163,6 +164,7 @@ 
#define RVG_MATCH_AUIPC		(RVG_OPCODE_AUIPC)

#define RVG_MATCH_JALR		(RV_ENCODE_FUNCT3(JALR) | RVG_OPCODE_JALR)

#define RVG_MATCH_JAL		(RVG_OPCODE_JAL)

#define RVG_MATCH_FENCE		(RVG_OPCODE_FENCE)

#define RVG_MATCH_BEQ		(RV_ENCODE_FUNCT3(BEQ) | RVG_OPCODE_BRANCH)

#define RVG_MATCH_BNE		(RV_ENCODE_FUNCT3(BNE) | RVG_OPCODE_BRANCH)

#define RVG_MATCH_BLT		(RV_ENCODE_FUNCT3(BLT) | RVG_OPCODE_BRANCH)
@@ -182,6 +184,7 @@ 
#define RVG_MASK_AUIPC		(RV_INSN_OPCODE_MASK)

#define RVG_MASK_JALR		(RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)

#define RVG_MASK_JAL		(RV_INSN_OPCODE_MASK)

#define RVG_MASK_FENCE		(RV_INSN_OPCODE_MASK)

#define RVC_MASK_C_JALR		(RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)

#define RVC_MASK_C_JR		(RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)

#define RVC_MASK_C_JAL		(RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
@@ -233,6 +236,13 @@ __RISCV_INSN_FUNCS(c_bnez, RVC_MASK_C_BNEZ, RVC_MATCH_C_BNEZ) 
__RISCV_INSN_FUNCS(c_ebreak, RVC_MASK_C_EBREAK, RVC_MATCH_C_EBREAK)

__RISCV_INSN_FUNCS(ebreak, RVG_MASK_EBREAK, RVG_MATCH_EBREAK)

__RISCV_INSN_FUNCS(sret, RVG_MASK_SRET, RVG_MATCH_SRET)

__RISCV_INSN_FUNCS(fence, RVG_MASK_FENCE, RVG_MATCH_FENCE);



/* special case to catch _any_ system instruction */

static __always_inline bool riscv_insn_is_system(u32 code)

{

	return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_SYSTEM;

}



/* special case to catch _any_ branch instruction */

static __always_inline bool riscv_insn_is_branch(u32 code)

arch/riscv/kernel/probes/simulate-insn.h

+0 −3
Original line number Diff line number Diff line
@@ -12,9 +12,6 @@ 
		}							\

	} while (0)



__RISCV_INSN_FUNCS(system,	0x7f, 0x73);

__RISCV_INSN_FUNCS(fence,	0x7f, 0x0f);



#define RISCV_INSN_SET_SIMULATE(name, code)				\

	do {								\

		if (riscv_insn_is_##name(code)) {			\