Commit 864788c0 authored by Amelie Delaunay's avatar Amelie Delaunay Committed by Vinod Koul
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dt-bindings: phy: phy-stm32-usbphyc: convert bindings to json-schema



Convert the STM32 USB PHY Controller (USBPHYC) bindings to DT schema format
using json-schema.

Signed-off-by: default avatarAmelie Delaunay <amelie.delaunay@st.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20201116171917.10447-1-amelie.delaunay@st.com


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 8eff8b4e
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STMicroelectronics STM32 USB HS PHY controller

The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
switch. It controls PHY configuration and status, and the UTMI+ switch that
selects either OTG or HOST controller for the second PHY port. It also sets
PLL configuration.

USBPHYC
      |_ PLL
      |
      |_ PHY port#1 _________________ HOST controller
      |                    _                 |
      |                  / 1|________________|
      |_ PHY port#2 ----|   |________________
      |                  \_0|                |
      |_ UTMI switch_______|          OTG controller


Phy provider node
=================

Required properties:
- compatible: must be "st,stm32mp1-usbphyc"
- reg: address and length of the usb phy control register set
- clocks: phandle + clock specifier for the PLL phy clock
- #address-cells: number of address cells for phys sub-nodes, must be <1>
- #size-cells: number of size cells for phys sub-nodes, must be <0>

Optional properties:
- assigned-clocks: phandle + clock specifier for the PLL phy clock
- assigned-clock-parents: the PLL phy clock parent
- resets: phandle + reset specifier

Required nodes: one sub-node per port the controller provides.

Phy sub-nodes
==============

Required properties:
- reg: phy port index
- phy-supply: phandle to the regulator providing 3V3 power to the PHY,
	      see phy-bindings.txt in the same directory.
- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY
  port#1 and must be <1> for PHY port#2, to select USB controller


Example:
		usbphyc: usb-phy@5a006000 {
			compatible = "st,stm32mp1-usbphyc";
			reg = <0x5a006000 0x1000>;
			clocks = <&rcc_clk USBPHY_K>;
			resets = <&rcc_rst USBPHY_R>;
			#address-cells = <1>;
			#size-cells = <0>;

			usbphyc_port0: usb-phy@0 {
				reg = <0>;
				phy-supply = <&vdd_usb>;
				vdda1v1-supply = <&reg11>;
				vdda1v8-supply = <&reg18>
				#phy-cells = <0>;
			};

			usbphyc_port1: usb-phy@1 {
				reg = <1>;
				phy-supply = <&vdd_usb>;
				vdda1v1-supply = <&reg11>;
				vdda1v8-supply = <&reg18>
				#phy-cells = <1>;
			};
		};
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: STMicroelectronics STM32 USB HS PHY controller binding

description:

  The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
  switch. It controls PHY configuration and status, and the UTMI+ switch that
  selects either OTG or HOST controller for the second PHY port. It also sets
  PLL configuration.

  USBPHYC
  |_ PLL
  |
  |_ PHY port#1 _________________ HOST controller
  |                   __                 |
  |                  / 1|________________|
  |_ PHY port#2 ----|   |________________
  |                  \_0|                |
  |_ UTMI switch_______|          OTG controller

maintainers:
  - Amelie Delaunay <amelie.delaunay@st.com>

properties:
  compatible:
    const: st,stm32mp1-usbphyc

  reg:
    maxItems: 1

  clocks:
    maxItems: 1

  resets:
    maxItems: 1

  "#address-cells":
    const: 1

  "#size-cells":
    const: 0

#Required child nodes:

patternProperties:
  "^usb-phy@[0|1]$":
    type: object
    description:
      Each port the controller provides must be represented as a sub-node.

    properties:
      reg:
        description: phy port index.
        maxItems: 1

      phy-supply:
        description: regulator providing 3V3 power supply to the PHY.

      vdda1v1-supply:
        description: regulator providing 1V1 power supply to the PLL block

      vdda1v8-supply:
        description: regulator providing 1V8 power supply to the PLL block

      "#phy-cells":
        enum: [ 0x0, 0x1 ]

    allOf:
      - if:
          properties:
            reg:
              const: 0
        then:
          properties:
            "#phy-cells":
              const: 0
        else:
          properties:
            "#phy-cells":
              const: 1
              description:
                The value is used to select UTMI switch output.
                0 for OTG controller and 1 for Host controller.

    required:
      - reg
      - phy-supply
      - vdda1v1-supply
      - vdda1v8-supply
      - "#phy-cells"

    additionalProperties: false

required:
  - compatible
  - reg
  - clocks
  - "#address-cells"
  - "#size-cells"
  - usb-phy@0
  - usb-phy@1

additionalProperties: false

examples:
  - |
    #include <dt-bindings/clock/stm32mp1-clks.h>
    #include <dt-bindings/reset/stm32mp1-resets.h>
    usbphyc: usbphyc@5a006000 {
        compatible = "st,stm32mp1-usbphyc";
        reg = <0x5a006000 0x1000>;
        clocks = <&rcc USBPHY_K>;
        resets = <&rcc USBPHY_R>;
        #address-cells = <1>;
        #size-cells = <0>;

        usbphyc_port0: usb-phy@0 {
            reg = <0>;
            phy-supply = <&vdd_usb>;
            vdda1v1-supply = <&reg11>;
            vdda1v8-supply = <&reg18>;
            #phy-cells = <0>;
        };

        usbphyc_port1: usb-phy@1 {
            reg = <1>;
            phy-supply = <&vdd_usb>;
            vdda1v1-supply = <&reg11>;
            vdda1v8-supply = <&reg18>;
            #phy-cells = <1>;
        };
    };
...