Commit 862a876c authored by Chris Park's avatar Chris Park Committed by Alex Deucher
Browse files

drm/amd/display: Correct Slice reset calculation 



[Why]
Once DSC slice cannot fit pixel clock, we incorrectly
reset min slices to 0 and allow max slice to operate,
even when max slice itself cannot fit the pixel clock
properly.

[How]
Change the sequence such that we correctly determine
DSC is not possible when both min slices and max
slices cannot fit pixel clock per slice.

Reviewed-by: default avatarWenjing Liu <Wenjing.Liu@amd.com>
Acked-by: default avatarAlex Hung <alex.hung@amd.com>
Signed-off-by: default avatarChris Park <Chris.Park@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent dda81d97

drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

+2 −2
Original line number Diff line number Diff line
@@ -864,11 +864,11 @@ static bool setup_dsc_config( 
		min_slices_h = inc_num_slices(dsc_common_caps.slice_caps, min_slices_h);

	}



	is_dsc_possible = (min_slices_h <= max_slices_h);



	if (pic_width % min_slices_h != 0)

		min_slices_h = 0; // DSC TODO: Maybe try increasing the number of slices first?



	is_dsc_possible = (min_slices_h <= max_slices_h);



	if (min_slices_h == 0 && max_slices_h == 0)

		is_dsc_possible = false;