Commit 861e58c8 authored by Zong-Zhe Yang's avatar Zong-Zhe Yang Committed by Kalle Valo
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rtw89: extract modules by chipset



We are planning to support more chipsets, e.g. 8852C. Before that, we
consider architecutre to handle multiple kinds of chipsets. Obviosuly,
based on original design, rtw89_core module will have large size even
if there is only one chipset under running. It is because all chipset
related things are put in rtw89_core now. To reduce such overhead, we
extract modules of rtw89 and adjust dependencies between modules.

The following assumes that 8852AE, 8852AU, and 8852CE are all supported,
we describe the difference before and after extraction.

[Before extraction]
                                             -------------
       |------------------------------------ | rtw89_usb |
       V                                     -------------
---------------------------------------      -------------
| rtw89_core (including 8852A, 8852C) | <--- | rtw89_pci |
---------------------------------------      -------------
The data of 8852A and 8852C are built in rtw89_core.
And rtw89_pci is the entry of 8852AE and 8852CE.
And rtw89_usb is the entry of 8852AU.

[After extraction]
                    -------------           ----------------
       |----------- | rtw89_usb | <-------- | rtw89_8852au |
       |            -------------           ----------------
       V            ---------------                |
--------------      |             | <---------------
| rtw89_core | <--- | rtw89_8852a |
--------------      |             | <---------------
   ^   ^            ---------------                |
   |   |            -------------           ----------------
   |   |            |           | <-------- | rtw89_8852ae |
   |   |----------- | rtw89_pci |           ----------------
   |                |           | <-----------------
   |                -------------                  |
   |                ---------------         ----------------
   |--------------- | rtw89_8852c | <------ | rtw89_8852ce |
                    ---------------         ----------------
The data of 8852A/8852C is extracted to rtw89_8852a/rtw89_8852c.
And rtw89_pci/rtw89_usb handles only common flow of pci/usb bus.
Finally, 8852AE, 8852AU, and 8852CE have individual entry modules,
i.e. rtw89_8852ae, rtw89_8852au, and rtw89_8852ce correspondingly.

Signed-off-by: default avatarZong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20211221025828.25092-1-pkshih@realtek.com
parent 3898da3b
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+4 −0
Original line number Diff line number Diff line
@@ -16,11 +16,15 @@ config RTW89_CORE
config RTW89_PCI
	tristate

config RTW89_8852A
	tristate

config RTW89_8852AE
	tristate "Realtek 8852AE PCI wireless network adapter"
	depends on PCI
	select RTW89_CORE
	select RTW89_PCI
	select RTW89_8852A
	help
	  Select this option will enable support for 8852AE chipset

+9 −4
Original line number Diff line number Diff line
@@ -6,10 +6,6 @@ rtw89_core-y += core.o \
		mac.o \
		phy.o \
		fw.o \
		rtw8852a.o \
		rtw8852a_table.o \
		rtw8852a_rfk.o \
		rtw8852a_rfk_table.o \
		cam.o \
		efuse.o \
		regd.o \
@@ -18,6 +14,15 @@ rtw89_core-y += core.o \
		ps.o \
		ser.o

obj-$(CONFIG_RTW89_8852A) += rtw89_8852a.o
rtw89_8852a-objs := rtw8852a.o \
		    rtw8852a_table.o \
		    rtw8852a_rfk.o \
		    rtw8852a_rfk_table.o

obj-$(CONFIG_RTW89_8852AE) += rtw89_8852ae.o
rtw89_8852ae-objs := rtw8852ae.o

rtw89_core-$(CONFIG_RTW89_DEBUG) += debug.o

obj-$(CONFIG_RTW89_PCI) += rtw89_pci.o
+1 −0
Original line number Diff line number Diff line
@@ -4370,6 +4370,7 @@ void rtw89_btc_ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_map,
		rtwdev->is_bt_iqk_timeout = true;
	}
}
EXPORT_SYMBOL(rtw89_btc_ntfy_wl_rfk);

struct rtw89_btc_wl_sta_iter_data {
	struct rtw89_dev *rtwdev;
+4 −4
Original line number Diff line number Diff line
@@ -15,7 +15,6 @@
struct rtw89_dev;

extern const struct ieee80211_ops rtw89_ops;
extern const struct rtw89_chip_info rtw8852a_chip_info;

#define MASKBYTE0 0xff
#define MASKBYTE1 0xff00
@@ -421,9 +420,6 @@ enum rtw89_regulation_type {
	RTW89_REGD_NUM,
};

extern const u8 rtw89_rs_idx_max[RTW89_RS_MAX];
extern const u8 rtw89_rs_nss_max[RTW89_RS_MAX];

struct rtw89_txpwr_byrate {
	s8 cck[RTW89_RATE_CCK_MAX];
	s8 ofdm[RTW89_RATE_OFDM_MAX];
@@ -2247,6 +2243,10 @@ struct rtw89_chip_info {
	u8 ps_mode_supported;
};

struct rtw89_driver_info {
	const struct rtw89_chip_info *chip;
};

enum rtw89_hcifc_mode {
	RTW89_HCIFC_POH = 0,
	RTW89_HCIFC_STF = 1,
+25 −10
Original line number Diff line number Diff line
@@ -481,9 +481,10 @@ int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err)
}
EXPORT_SYMBOL(rtw89_mac_set_err_status);

const struct rtw89_hfc_prec_cfg rtw_hfc_preccfg_pcie = {
const struct rtw89_hfc_prec_cfg rtw89_hfc_preccfg_pcie = {
	2, 40, 0, 0, 1, 0, 0, 0
};
EXPORT_SYMBOL(rtw89_hfc_preccfg_pcie);

static int hfc_reset_param(struct rtw89_dev *rtwdev)
{
@@ -1136,49 +1137,58 @@ static int rtw89_mac_sys_init(struct rtw89_dev *rtwdev)
}

/* PCIE 64 */
const struct rtw89_dle_size wde_size0 = {
const struct rtw89_dle_size rtw89_wde_size0 = {
	RTW89_WDE_PG_64, 4095, 1,
};
EXPORT_SYMBOL(rtw89_wde_size0);

/* DLFW */
const struct rtw89_dle_size wde_size4 = {
const struct rtw89_dle_size rtw89_wde_size4 = {
	RTW89_WDE_PG_64, 0, 4096,
};
EXPORT_SYMBOL(rtw89_wde_size4);

/* PCIE */
const struct rtw89_dle_size ple_size0 = {
const struct rtw89_dle_size rtw89_ple_size0 = {
	RTW89_PLE_PG_128, 1520, 16,
};
EXPORT_SYMBOL(rtw89_ple_size0);

/* DLFW */
const struct rtw89_dle_size ple_size4 = {
const struct rtw89_dle_size rtw89_ple_size4 = {
	RTW89_PLE_PG_128, 64, 1472,
};
EXPORT_SYMBOL(rtw89_ple_size4);

/* PCIE 64 */
const struct rtw89_wde_quota wde_qt0 = {
const struct rtw89_wde_quota rtw89_wde_qt0 = {
	3792, 196, 0, 107,
};
EXPORT_SYMBOL(rtw89_wde_qt0);

/* DLFW */
const struct rtw89_wde_quota wde_qt4 = {
const struct rtw89_wde_quota rtw89_wde_qt4 = {
	0, 0, 0, 0,
};
EXPORT_SYMBOL(rtw89_wde_qt4);

/* PCIE SCC */
const struct rtw89_ple_quota ple_qt4 = {
const struct rtw89_ple_quota rtw89_ple_qt4 = {
	264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,
};
EXPORT_SYMBOL(rtw89_ple_qt4);

/* PCIE SCC */
const struct rtw89_ple_quota ple_qt5 = {
const struct rtw89_ple_quota rtw89_ple_qt5 = {
	264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,
};
EXPORT_SYMBOL(rtw89_ple_qt5);

/* DLFW */
const struct rtw89_ple_quota ple_qt13 = {
const struct rtw89_ple_quota rtw89_ple_qt13 = {
	0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0
};
EXPORT_SYMBOL(rtw89_ple_qt13);

static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev,
						   enum rtw89_qta_mode mode)
@@ -2116,6 +2126,7 @@ int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,

	return 0;
}
EXPORT_SYMBOL(rtw89_mac_stop_sch_tx);

int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u16 tx_en)
{
@@ -2127,6 +2138,7 @@ int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u16 tx_en)

	return 0;
}
EXPORT_SYMBOL(rtw89_mac_resume_sch_tx);

static u16 rtw89_mac_dle_buf_req(struct rtw89_dev *rtwdev, u16 buf_len,
				 bool wd)
@@ -3192,6 +3204,7 @@ bool rtw89_mac_get_txpwr_cr(struct rtw89_dev *rtwdev,

	return false;
}
EXPORT_SYMBOL(rtw89_mac_get_txpwr_cr);

int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)
{
@@ -3216,6 +3229,7 @@ int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable)

	return ret;
}
EXPORT_SYMBOL(rtw89_mac_cfg_ppdu_status);

void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx)
{
@@ -3349,6 +3363,7 @@ int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex

	return 0;
}
EXPORT_SYMBOL(rtw89_mac_coex_init);

int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev,
		      const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
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